A 12-bit successive-approximation-type ADC with digital error correction

Bacrania, K.

doi:10.1109/jssc.1986.1052644

Cited by 34 publications

(12 citation statements)

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“…Therefore, a dynamic error correction is introduced, which adds a stage of redundancy. Several different forms of error correction units have been described in previous publications (Ogawa et al , 2008;Bacrania , 1986;Cho et al , 2009). The schematic of the improved capacitor array can be seen in Fig.…”

Section: Digital Trimmingmentioning

confidence: 99%

Implementation of a digital trim scheme for SAR ADCs

et al. 2013

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Abstract. Successive approximation register (SAR) analogto-digital Converters (ADC) are based on a capacitive digitalto-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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Section: Digital Trimmingmentioning

confidence: 99%

Implementation of a digital trim scheme for SAR ADCs

et al. 2013

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“…Multi-step architectures include two-step [25], sub-ranging [26], pipelined [27], and successive approximation [28]. The one-step flash or "direct" converter topology [29,30] converter on the number of bits limit its use to resolutions below 10 bits.…”

Section: Comparison With Direct Digital Conversionmentioning

confidence: 99%

High-Speed, High-Resolution Analog Waveform Sampling in VLSI Technology

Haller¹

1998

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Switched-capacitor analog memories are well-suited to a number of applications where a continuous digitization of analog signals is not needed. In data acquisition systems based on the use of an analog memory, the input waveforms are sampled and stored at a high rate for a limited period of time, and the analog samples are then retrieved at a lower rate and digitized with a slow ADC before new waveforms are acquired. The advantages of using an analog memory are lower overall power dissipation and cost, higher density and reliability, and potentially superior performance. The analog memory essentially exploits the fact that the sampling and storage of samples in a bank of analog memory cells can be accomplished at a higher rate and with a greater precision than direct digital conversion.This dissertation examines the important components of an analog memory in detail and investigates their use in a number of architectures. The research has led to the design of an analog memory that can acquire analog waveforms at sampling rates of several hundred MHz with a dynamic range and linearity of more than 12 bits, without the need for elaborate calibration and correction procedures. This is accomplished by means of a new memory architecture that results in memory cell pedestals and sampling times that are independent of the signal level, as well as cell gains that are insensitive to component sizes. The write address control for this memory has been realized with an inverter delay chain that provides substantially higher performance with respect to sampling rate and timing accuracy than other published approaches.Based upon the concepts developed in this work, an experimental analog memory was designed and integrated in a 2-µm CMOS process. Extensive measurements of this proto-

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“…Any inaccuracy on the performance of these circuit blocks substantially affects the accuracy of the ADC. Successive Approximation ADC [5] is of such structures which its reliability and accuracy is directly related to the performance of an internal Digital to Analog Converter (DAC). Integrating ADC has extensively been used for IC development due to its superior resolution; however its conversion rate is considerably slower than the other ADC structures and any non-ideality affecting the internal capacitor, resistor as well as the clocking frequency of the internal counter, affects the linearity of the ADC structure.…”

Section: Introductionmentioning

confidence: 99%