High-Speed, High-Resolution Analog Waveform Sampling in VLSI Technology

Haller, G.

doi:10.2172/10132

Cited by 8 publications

(4 citation statements)

References 45 publications

(56 reference statements)

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“…Even so, the SCA-based schemes still compare favorably. ZEUS [12] RD2 [13] Kleinfelder [14] Haller [15] ADeLine1 [11] DSC/DRS [16] AD9410 [17] CLC5957…”

Section: High Speed Transient Digitizersmentioning

confidence: 99%

Monolithic multi-channel GSa/s transient waveform recorder for measuring radio emissions from high energy particle cascades

2003

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A number of particle astrophysics initiatives to exploit radio emission from high energy particle cascades require highfrequency sampling of antenna array signals. Nyquist-limited sampling of GHz frequency radio signals for an antenna array may be accomplished by commercially available test units. However, these technologies are incompatible with the size, power and cost constraints of long-duration balloon or satellite flight. Taking advantage of low trigger rates for such arrays, high resolution digitization may be performed a postori, at much slower speed and power, on waveforms stored in analog storage cells. This paper presents the design and performance simulation of a multichannel CMOS VLSI ASIC named STRAW (Self-Triggered Recorder for Analog Waveforms), optimized for low duty-cycle, high sampling frequency operation.

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“…Even so, the SCA-based schemes still compare favorably. ZEUS [12] RD2 [13] Kleinfelder [14] Haller [15] ADeLine1 [11] DSC/DRS [16] AD9410 [17] CLC5957…”

Section: High Speed Transient Digitizersmentioning

confidence: 99%

Monolithic multi-channel GSa/s transient waveform recorder for measuring radio emissions from high energy particle cascades

2003

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“…5 [13]. Several alternative solutions have been explored, for example, in [14], but we think that the one described here is the best to achieve a high dynamic range with the limited power supply voltage available in a deep submicron process. A voltage write-voltage read architecture has been chosen, to minimize the sensitivity to the capacitor value.…”

Section: Memory Descriptionmentioning

confidence: 99%

“…The dynamic range is defined as the ratio of the input voltage range to the minimum detectable signal [14], which can be considered equal to the input referred rms noise voltage. From our measurements, values of a dynamic range between 11 and 12 bits are found.…”

Section: A Preirradiationmentioning

confidence: 99%

A large dynamic range radiation-tolerant analog memory in a quarter-micron CMOS technology

Anelli

Anghinolfi

Rivetti

2001

IEEE Trans. Nucl. Sci.

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Abstract-An analog memory prototype containing 8 128 cells has been designed in a commercial quarter-micron CMOS process. The aim of this work is to investigate the possibility of designing large dynamic range mixed-mode switched capacitor circuits for high-energy physics (HEP) applications in deep submicron CMOS technologies. Special layout techniques have been used to make the circuit radiation tolerant. The memory cells employ gate-oxide capacitors for storage, permitting a very high density. A voltage write-voltage read architecture has been chosen to minimize the sensitivity to absolute capacitor values. The measured input voltage range is 2.3 V (the power supply voltage is equal to 2.5 V), with a linearity of almost 8 bits over 2 V. The dynamic range is more than 11 bits. The pedestal variation is 0.5 mV peak-to-peak. The noise measured, which is dominated by the noise of the measurement setup, is around 0.8 mV rms. The characteristics of the memory have been measured before irradiation and after 100 kGy (SiO 2 ), and they do not degrade after irradiation.

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“…It is a switched capacitor array with a Voltage Sampling-Voltage Transfer topology [4] [5]. The memory samples three channels simultaneously at 200 Msamples per second.…”

Section: The Lira Analogue Memorymentioning

confidence: 99%

A VLSI Full Custom ASIC Front End for the Optical Module of NEMO Underwater Neutrino Detector

Presti¹,

Randazzo²,

Caponetto³

IEEE Nuclear Science Symposium Conference Record, 2005

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The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contain the telescope optical sensors, as a full-custom Very Large Scale Integration (VLSI) Action Specific Integrated Circuit (ASIC). The advantages of this solution are manifold. The most important are low power consumption and the preanalysis and opportune reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given. The chips produced will be described and the test measurements performed will be shown.

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High-Speed, High-Resolution Analog Waveform Sampling in VLSI Technology

Cited by 8 publications

References 45 publications

Monolithic multi-channel GSa/s transient waveform recorder for measuring radio emissions from high energy particle cascades

Monolithic multi-channel GSa/s transient waveform recorder for measuring radio emissions from high energy particle cascades

A large dynamic range radiation-tolerant analog memory in a quarter-micron CMOS technology

A VLSI Full Custom ASIC Front End for the Optical Module of NEMO Underwater Neutrino Detector

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