2003
DOI: 10.1117/12.458018
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Monolithic multi-channel GSa/s transient waveform recorder for measuring radio emissions from high energy particle cascades

Abstract: A number of particle astrophysics initiatives to exploit radio emission from high energy particle cascades require highfrequency sampling of antenna array signals. Nyquist-limited sampling of GHz frequency radio signals for an antenna array may be accomplished by commercially available test units. However, these technologies are incompatible with the size, power and cost constraints of long-duration balloon or satellite flight. Taking advantage of low trigger rates for such arrays, high resolution digitization… Show more

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Cited by 9 publications
(11 citation statements)
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“…The ASIC design presented here is the natural evolution of a series of ASICs that have been developed for radio neutrino detection [7,8], recording of photodetector output with precision timing [9,10], and highly integrated photodetector readout [11]. In order to meet the demands of next-generation IACT arrays for very-high-energy (VHE) gamma-ray astronomy, we draw upon this ASIC development experience to optimize the design of such highly integrated, cost-effective readout.…”
Section: Introductionmentioning
confidence: 99%
“…The ASIC design presented here is the natural evolution of a series of ASICs that have been developed for radio neutrino detection [7,8], recording of photodetector output with precision timing [9,10], and highly integrated photodetector readout [11]. In order to meet the demands of next-generation IACT arrays for very-high-energy (VHE) gamma-ray astronomy, we draw upon this ASIC development experience to optimize the design of such highly integrated, cost-effective readout.…”
Section: Introductionmentioning
confidence: 99%
“…The basic design for node electronics centers on the use of a switched-capacitor array (SCA) transient digitizer, which is only read out and sent to the surface when the local node is triggered; a prototype of the basic design, which uses Gigabit ethernet on one fiber per node to the surface, is described by G. Varner et al [25,26].…”
Section: A Application To Detector Modelingmentioning
confidence: 99%
“…All have been fabricated in the TSMC 0.25µm CMOS (LO) process and have been packaged in a 100pin plastic TQFP package. Economics and package performance simulations [11] drove this decision. BGA packages were considered and may be used in the future to reduce the contribution due to lead inductance, however all test results are shown for this same 16.6 x 16.6 mm plastic package.…”
Section: Architectural Detailsmentioning
confidence: 99%
“…Layout of the LAB1 ASIC quite directly follows the arrangement of the functional blocks in the schematic diagram. While efforts were made to optimize the coupling of the input signal based on earlier efforts with the STRAW [11] architecture, the choice of LAB1 input structure represented a compromise, as shown in Fig. 4.…”
Section: Architectural Detailsmentioning
confidence: 99%