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The DNL performance of the last generation of Analog-to-Digital Converter (A/D Converter, ADC) based on the principle of SAR (successive-approximation register) was limited by a small amount of spikes at particular codes that changed with varying conversion rate, so that these errors were called 'dynamic errors'. These errors always appeared in pairs: a long code followed by a short code at very particular transitions. This paper is discussing the root source and techniques that fix the problem. These techniques were implemented and verified on silicon.

Abstract. Successive approximation register (SAR) analogto-digital Converters (ADC) are based on a capacitive digitalto-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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