Methods to eliminate dynamic errors in high-performance SAR A/D converter

Ohnhaeuser, Frank; Huemer, Mario

doi:10.1109/iscas.2008.4541938

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Digital Trimming1

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Cited by 5 publications

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“…5. The dynamic error correction consists of two capacitors C DUP and C DDWN (Ohnhaeuser and Huemer , 2008;Srinivasan and Godbole , 2002). In this example, the dynamic error correction is placed between the second and the third bit decision.…”

Section: Digital Trimmingmentioning

confidence: 99%

Implementation of a digital trim scheme for SAR ADCs

et al. 2013

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Abstract. Successive approximation register (SAR) analogto-digital Converters (ADC) are based on a capacitive digitalto-analog converter (CDAC) (McCreary and Gray, 1975). The capacitor mismatch in the capacitor array of the CDAC impacts the differential non-linearity (DNL) of the ADC directly. In order to achieve a transfer function without missing codes, trimming of the capacitor array becomes necessary for SAR ADCs with a resolution of more than 12 bit. This article introduces a novel digital approach for trimming. DNL measurements of an 18 bit SAR ADC show that digital trimming allows the same performance as analog trimming. Digital trimming however reduces the power consumption of the ADC, the die size and the required time for the production test.

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Section: Digital Trimmingmentioning

confidence: 99%