A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications

Feldman, Asaf; Boser, Bernhard E.; Gray, P.R.

doi:10.1109/4.720392

Cited by 63 publications

(22 citation statements)

References 20 publications

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“…Some designs use a single common-mode-feed-back (CMFB) circuit [2], where the common-mode voltage of the second stage is sensed and then put through a sign inversion circuit (often a current mirror, which consumes extra power) to control the bias in the first stage. In this implementation we use two separate CMFB circuits.…”

Section: Common-mode Feedbackmentioning

confidence: 99%

“…With a signal band of 1 MHz and oversampling ratio of 16 (which is already relatively low), the modulator must sampIe at 32MHz. Many researches have been done to increase the signal band that can be converted by sigma delta modulators [1,2], and obviously that the essential task is to design a high performance operational amplifier which is used in switch capacitor integmtors. The amplifier should have a high OC gain, large bandwidth, large slew rate (driving capability) and large output swing.…”

Section: Introductionmentioning

confidence: 99%

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A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process

Tenhunen

2000

VLSI: Systems on a Chip

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Abstract:An operational amplifier designcd with O.35um CMOS teehnology is prcsented. All the transistors are realized with minimum or near-minimum ehannel length. As thc short ehannel length causcs performance degradation, a proper operational amplifier structure is sclected to compensate the performance degradation. The op amp is designed to meet the requirement of high-speed high-resolution sigma delta modulators. It has a folded-cascode first stage and a class-A output stage. lt features a DC gain of 78dB, an openloop unity-gain frequency of 266MHZ, a slew rate of 650V/us, and consumes IO.2mW from a +/-1.5V power supply. High level simulation is uscd to evaluatc the OT A performance in sigma delta modulators.

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Section: Common-mode Feedbackmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Design of Operational Amplifiers for Sigma Delta Modulators using 0.35um CMOS Process

Tenhunen

2000

VLSI: Systems on a Chip

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“…It will, though, increase current consumption and noise. In SC circuits a capacitive level shifter, which does not have these disadvantages, can be utilized [174]. Figure 7.9 (a) shows the principle of a switched capacitor level shifter, which is based on a capacitor that is periodically charged to the desired offset voltage (V B1 −V B2 ).…”

Section: High-gain First Stage and Rail-to-rail Output Stagementioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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“…2b. The mathematical analysis of voltage gain from power supply to regulator output in (6) shows that the MOSFET compensation capacitor bank C M1 and C M2 introduces a negative time constant at node X2b and pushes the zero to high frequencies, while it does not affect the main frequency response of the error amplifier. 1+ gmpr p gm2…”

Section: Power Supply Rejection Ratio (Psrr)mentioning

confidence: 99%

“…The settling behavior is characterized by its step response and its associated settling error [6]. The percentage settling error at the regulator output and at a specific time t s is expressed as follows:…”

Section: Clg Mpmentioning

confidence: 99%