A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Li, Weitao; Li, Fule; Liu, Jia; Li, Hongyu; Wang, Zhihua

doi:10.1109/asscc.2017.8240257

Cited by 8 publications

(5 citation statements)

References 10 publications

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“…V os,in = g mP g mN V os,P + V os,N (14) where the subscripts N and P denote NMOS and PMOS, respectively.…”

Section: Design Of the Offset Trimming Circuitmentioning

confidence: 99%

“…In [13], a four-stage static comparator combining the OOS and the CDS techniques was used to eliminate the offset caused by the input level and was applied in a two-step single-slope (SS) ADC for CMOS image sensors with a high frame rate. The dynamic latched comparator proposed in [14] adopted the IOS technique to increase the conversion linearity and was applied in a pipelined sub-ranging SAR ADC. In [15], IOS technology and neutralization technology were adopted in a quantizer that consisted of 15 comparators and applied in a sigma-delta ADC dedicated to automotive control systems to reduce the offset voltage and kickback noise, respectively.…”

Section: Introductionmentioning

confidence: 99%

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Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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A novel self-calibration comparator for a 12-bit 2.5 MSPS successive approximation register analog-to-digital converter (SAR ADC) applied in a touch microcontroller unit (MCU) with small area, high precision, fast response speed, and low-voltage detection is proposed in this paper. A combination of input/output offset storage (IOS/OOS) and an offset trimming circuit was employed to reduce the offset of the cascade preamplifier and the operational transconductance amplifier (OTA), a novel offset trimming circuit with a 5-bit digital controller was designed to further reduce the residual offset voltage, and an improved self-calibration technology was also implemented to compensate the conversion error in SAR ADC system to a minimum. Simulation and measured results show that the input-referred offset calibrating range is ±9.15 mV at 0.61 mV/step, the low-voltage detection of SAR ADC is realized by compensating the conversion error to a minimum, and the effective number of bits (ENOB) and figure of merit (FoM) at 5 V supply and 2.5 M/s rate in the 12-bit SAR ADC with a 95 nm CMOS are 11.33 bits and 726.6 fJ/conversion-step, respectively. The proposed self-calibration comparator applied in the SAR ADC system can automatically eliminate the offset voltage caused by nonidealities and meet the requirements of the touch MCU.

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“…V os,in = g mP g mN V os,P + V os,N (14) where the subscripts N and P denote NMOS and PMOS, respectively.…”

Section: Design Of the Offset Trimming Circuitmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Tang

Wang

et al. 2023

Electronics

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show abstract

“…The spikes that usually appear in SAR converter full-range non-linearity results could be softened by applying a dynamic element matching (DEM) algorithm [26] to a partially thermometer-coded C-DAC [27]. With comparator power dissipation and noise figure being critical for circuit performance, its architecture must be carefully designed [28][29][30].…”

Section: Introductionmentioning

confidence: 99%

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

Bontems

Dzahini

2023

Chips

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This paper presents a design methodology for a low-power, low-chip-area, and high-resolution successive approximations register (SAR) analog-to-digital converter (ADC). The proposed method includes a segmented capacitive DAC (C-DAC) to reduce the power consumption and the total area. An embedded self-calibration algorithm based on a set of trimming capacitors was applied alongside a dynamic element matching (DEM) procedure to control the inherent linearity issues caused by the process mismatch. The SAR ADC and each additional algorithm were modeled in MATLAB to show their efficiency. Finally, a simple methodology was developed to allow for the fast estimation of signal-to-noise ratios (SNRs) without any FFT calculation.

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“…With the scaling down of the transistor size, the single-channel SAR ADCs [6][7][8][9][10] can achieve hundreds of MS/s sampling rate with resolution no less than 10bit. Meanwhile, the hybrid structure pipelined SARs [11][12][13] are popular to realize the high-speed mediumresolution ADC. In the past few years, many power-efficient switching schemes [14][15][16][17][18][19][20][21] are proposed.…”

Section: Introductionmentioning

confidence: 99%

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

Huang

Meng

et al. 2021

IEICE Electron. Express

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In this paper, a high-speed low-power SAR ADC is designed. In this prototype, an improved switching scheme combined with the optimized attenuation capacitor architecture is proposed, showing more power efficiency and is more suitable for high-speed data converters. Meanwhile, an improved synchronous timing strategy is employed, achieving flexible time allocation of DAC settling and comparison in each bit-cycle. In addition, a two-stage non-tail-current-source and single-phaseclock comparator is proposed with more power-efficiency and compatible resolving time. The prototype ADC is fabricated in a 40nm CMOS technology and occupies an active area of 0.04mm 2 . An SNDR of 57.18dB and an SFDR of 75.29dB are achieved with the Nyquist rate input at a sampling rate of 160MS/s, consuming 1.3mW at 1.1V supply voltage.

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A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator

Cited by 8 publications

References 10 publications

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Design of Self-Calibration Comparator for 12-Bit SAR ADCs

Methodology for a Low-Power and Low-Circuit-Area 15-Bit SAR ADC Using Split-Capacitor Mismatch Compensation and a Dynamic Element Matching Algorithm

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

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