A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

Li, Shaolan; Qiao, Bing; Gandara, Miguel; Pan, David Z.; Sun, Nan

doi:10.1109/jssc.2018.2871081

Cited by 99 publications

(46 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…This is usually implemented using an on-chip PLL, which requires additional power consumption and die area. Various energy efficient ADCs have been described utilizing a hybrid structure, such as the noise-shaping SAR [53], which combines conversion techniques from both the SAR and sigma-delta ADCs and the VCO-SAR [54], which employs a SAR for conversion of the most significant bits (MSBs) and a VCObased Nyquist ADC for conversion of the least significant bits (LSBs). The combination of two different architectures provides a means of achieving both high resolution and low power consumption at high sample-rates.…”

Section: Introductionmentioning

confidence: 99%

Gated Pipelined Folding ADC-Based Low Power Sensor for Large-Scale Radiometric Partial Discharge Monitoring

et al. 2020

View full text Add to dashboard Cite

Partial discharge is a well-established metric for condition assessment of high-voltage plant equipment. Traditional techniques for partial discharge detection involve physical connection of sensors to the device under observation, limiting sensors to monitoring of individual apparatus, and therefore, limiting coverage. Wireless measurement provides an attractive low-cost alternative. The measurement of the radiometric signal propagated from a partial discharge source allows for multiple plant items to be observed by a single sensor, without any physical connection to the plant. Moreover, the implementation of a large-scale wireless sensor network for radiometric monitoring facilitates a simple approach to high voltage fault diagnostics. However, accurate measurement typically requires fast data conversion rates to ensure accurate measurement of faults. The use of high-speed conversion requires continuous high-power dissipation, degrading sensor efficiency and increasing cost and complexity. Thus, we propose a radiometric sensor which utilizes a gated, pipelined, sample-and-hold based folding analogue-todigital converter structure that only samples when a signal is received, reducing the power consumption and increasing the efficiency of the sensor. A proof of concept circuit has been developed using discrete components to evaluate the performance and power consumption of the system.

show abstract

Section: Introductionmentioning

confidence: 99%

Gated Pipelined Folding ADC-Based Low Power Sensor for Large-Scale Radiometric Partial Discharge Monitoring

et al. 2020

View full text Add to dashboard Cite

show abstract

“…With the recent prolificacy of sensors, portable gadgets, implantable electronics and IoT (Internet of Things) devices, there are strong demands for low‐voltage, power‐efficient ADC circuits. Thanks to its simple structure, digital like switching operation, and the wide availability of small unit capacitors at advanced technology nodes, successive approximation register (SAR) ADC with using charge scaling (CS) capacitor arrays poses as an attractive design choice for these applications [1–23]. Traditionally, SAR ADCs implement the binary search algorithm and require N conversion cycles to produce an N ‐bit digital code, which potentially limits SAR ADC throughput.…”

Section: Introductionmentioning

confidence: 99%

“…To mitigate such challenges, asynchronous SAR ADC techniques [6, 7, 14, 15] have been proposed in literature. More recently, non‐binary search methods incorporating redundancy [16, 17] and noise shaping techniques [18, 19] have also been used in SAR ADC circuits for improving resolutions.…”

Section: Introductionmentioning

confidence: 99%

Accelerating low‐voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques

Nagabhushana

Wang

2020

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

This work presents techniques that effectively utilise comparator timing information to accelerate low-voltage successive approximation register (SAR) analogue-to-digital converter (ADC) operation. Compared to existing approaches that only exploit the prolonged comparator decision time in the events of metastability, the proposed techniques are effective in a broader voltage range and can extract more information about the voltages being compared. To cope with large variations associated with comparator delay, this work proposes robust timing measurement circuit, uncertainty-tolerant search algorithm and circuit adaptive tuning techniques. The adaptive tuning technique enables ADC to autonomously find voltage levels corresponding to the outputs of the timing measurement circuit as well as to adjust the uncertainty ranges used in the search algorithm. This eliminates the need of post-silicon calibration for the timing measurement circuits, which are typically required in existing approaches. The developed techniques are used in the design of a 9-bit 0.45 V SAR ADC circuit with a 130 nm complementary metal-oxide-semiconductor technology. Measurement results from the prototype chip indicate that for most input levels the proposed ADC completes conversion in six or seven conversion cycles. At 200 KS/s sampling rate, its power dissipation is 2.88 µW and it achieves a signal-to-noise distortion ratio of 50.66 dB with a figure of merit of 51.8 fJ/c.-s.

show abstract

“…High SNDR ADCs are widely used in mixed-signal system-on-chip (SoC) in the fields of both the industrial and the consumer applications. The SAR ADC is well known as a high energy efficiency ADC architecture for medium resolution, low or medium speed applications [1,2,3,4,5,6,7]. However, because the resolution of SAR ADC depends on the offset of comparator and the accuracy of capacitor array matching, it is difficult to realize the high resolution ADC in nanoscale CMOS technology.…”

Section: Introductionmentioning

confidence: 99%

“…IEICE Electronics Express, Vol 16,. No.12,[1][2][3][4][5][6] of 84.16 dB at −1.24 dBFS and −4.37 dBFS are achieved, respectively. The measurement results show that linear SNDR responses up to the full scale, and the dynamic range of 85 dB is achieved.…”

mentioning

confidence: 96%

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Pan

San

2019

IEICE Electron. Express

View full text Add to dashboard Cite

A proof-of-concept delta sigma AD modulator using dynamic analog components with simplified operation mode is designed and fabricated in 90 nm CMOS technology. The measurement results of the experimental prototype demonstrate the feasibility of the proposed modulator architecture which can guarantee the reset time for ring-amplifier and relax the speed requirement on the asynchronous SAR quantizer. The peak SNDR of 77.93 dB and SNR of 84.16 dB are achieved while a sinusoid −4 dBFS input is sampled at 14 MS/s with signal bandwidth of 109 kHz. The total analog power consumption of the prototype modulator is 720 µW under the supply voltage of 1.2 V.

show abstract

A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure

Cited by 99 publications

References 27 publications

Gated Pipelined Folding ADC-Based Low Power Sensor for Large-Scale Radiometric Partial Discharge Monitoring

Gated Pipelined Folding ADC-Based Low Power Sensor for Large-Scale Radiometric Partial Discharge Monitoring

Accelerating low‐voltage SAR ADC operation via comparator timing assisted and circuit adaptive tuning techniques

Experimental implementation of delta sigma AD modulator using dynamic analog components with simplified operation phase

Contact Info

Product

Resources

About