2020
DOI: 10.1109/tvlsi.2020.2997700
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A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices

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Cited by 5 publications
(15 citation statements)
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“…Resistant Multicore Platform With Effective Randomization Techniques; TVLSI June 2020 1423-1434 Yang, J., see Liu, C., 2469-2473Yang, J., see Shen, S., TVLSI Jan. 2020 Yang, K., see Zhang, R., TVLSI March 2020 620-633 Yang, K., see Wu, Y., 2658-2671 SHA-Less Pipelined ADC With Aperture Error Reduction; 2004-2013, see Zhu, C., 1953-1965 Yang, Y., see Liu, M., 1331-1335 Yang-Scharlotta, J., see Agnesina, A., 2055-2068 Yap, W., see Phoon, J., 2672-2684 Yarmand, R., Kamal, M., Afzali-Kusha, A., and Pedram, M., DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy; TVLSI Jan. 2020 273-286 Ye, M., Zheng, X., Li, Y., and Zhao, Y., A Low-Complexity Hybrid Readout Circuit for Lidar Receiver; TVLSI March 2020 828-832 Yektaei, M., and Ghaznavi-Ghoushchi, M.B., PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications; TVLSI Aug. 2020 1782-1795 Yepez, J., and Ko, S., Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks; TVLSI April 2020 853-863 Yi, Y., see Bai, K., TVLSI Jan. 2020 62-75 Yin, J., see Vitee, N., TVLSI March 2020 700-713 Yin, J., see Vitee, N., 1164-1174 Yin, S., Jiang, Z., Kim, M., Gupta, T., Seok, M., and Seo, J., Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks; TVLSI Jan. 2020 48-61 Yoo, C., see Kim, H., 1107-1117 Yoo, T., see Lu, L., TVLSI June 20201345-1356 Yoo, T., see Le, V.L., TVLSI Aug. 20201909-1919 Yoon, J.M., see Joo, H., 2708-2720 Yotsuyanagi, H., see Lu, S., TVLSI March 2020 634-645 You, X., see Ji, C., TVLSI July 2020 1703-1716 Ytterdal, T., see Late, E., 2223-2227 Yu, H., and Swaminathan, M., A Bit-Time-Dependent Model of I/O Drivers for Overclocking Analysis; 1630…”
Section: a Power Analysis Attackmentioning
confidence: 99%
“…Resistant Multicore Platform With Effective Randomization Techniques; TVLSI June 2020 1423-1434 Yang, J., see Liu, C., 2469-2473Yang, J., see Shen, S., TVLSI Jan. 2020 Yang, K., see Zhang, R., TVLSI March 2020 620-633 Yang, K., see Wu, Y., 2658-2671 SHA-Less Pipelined ADC With Aperture Error Reduction; 2004-2013, see Zhu, C., 1953-1965 Yang, Y., see Liu, M., 1331-1335 Yang-Scharlotta, J., see Agnesina, A., 2055-2068 Yap, W., see Phoon, J., 2672-2684 Yarmand, R., Kamal, M., Afzali-Kusha, A., and Pedram, M., DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy; TVLSI Jan. 2020 273-286 Ye, M., Zheng, X., Li, Y., and Zhao, Y., A Low-Complexity Hybrid Readout Circuit for Lidar Receiver; TVLSI March 2020 828-832 Yektaei, M., and Ghaznavi-Ghoushchi, M.B., PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications; TVLSI Aug. 2020 1782-1795 Yepez, J., and Ko, S., Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks; TVLSI April 2020 853-863 Yi, Y., see Bai, K., TVLSI Jan. 2020 62-75 Yin, J., see Vitee, N., TVLSI March 2020 700-713 Yin, J., see Vitee, N., 1164-1174 Yin, S., Jiang, Z., Kim, M., Gupta, T., Seok, M., and Seo, J., Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks; TVLSI Jan. 2020 48-61 Yoo, C., see Kim, H., 1107-1117 Yoo, T., see Lu, L., TVLSI June 20201345-1356 Yoo, T., see Le, V.L., TVLSI Aug. 20201909-1919 Yoon, J.M., see Joo, H., 2708-2720 Yotsuyanagi, H., see Lu, S., TVLSI March 2020 634-645 You, X., see Ji, C., TVLSI July 2020 1703-1716 Ytterdal, T., see Late, E., 2223-2227 Yu, H., and Swaminathan, M., A Bit-Time-Dependent Model of I/O Drivers for Overclocking Analysis; 1630…”
Section: a Power Analysis Attackmentioning
confidence: 99%
“…In addition to the aforementioned HGR systems [16]- [18] based on computing- intensive algorithms, some compact HGR systems [19], [20] adopt customized algorithms to achieve a balance between accuracy and power. However, the energyefficient features used in these systems limit the number of gesture types that can be recognized, therefore, constraining the applicable scenarios of the HGR systems.…”
Section: B Rgb Camera-based Hgr Systemsmentioning
confidence: 99%
“…However, the computation-intensive tasks, such as image processing and fingertip localization, were implemented on FPGA whose power was not included in the power analysis. Apart from the aforementioned HGR systems for complex HCI scenarios as in [33], the ultralow-power HGR systems [19], [20] utilizing lite signal processing algorithms have also been proposed. The system on chip (SoC) in [19] can recognize 8 dynamic gestures using the features of the projected histogram with an average accuracy of 90.6%.…”
Section: Pre-processingmentioning
confidence: 99%
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