A 13b-ENOB 173dB-FoM 2<sup>nd</sup>-order NS SAR ADC with passive integrators

Guo, Wenjuan; Zhuang, Haoyu; Sun, Nan

doi:10.23919/vlsic.2017.8008492

Cited by 42 publications

(17 citation statements)

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“…The noise shaping technique has been actively investigated to address the challenge [ 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 ]. This technique moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR).…”

Section: Introductionmentioning

confidence: 99%

“…Alternatively, a voltage–time–voltage converter can be used to achieve process-insensitive active residue processing [ 8 ]. Because there are two signal components, DAC output and filtered residue at the comparator input, the comparator with multi-input pairs is used [ 7 , 15 , 16 , 17 ]. To handle the small residue, the differential input pair for the residue is sized larger than the one other receiving the DAC output.…”

Section: Introductionmentioning

confidence: 99%

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An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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Herein, we present a noise shaping successive-approximation-register (SAR) analog-to-digital converter (ADC) with an embedded passive gain multiplication technique. The noise shaping moves the in-band quantization noise from the signal band to out-of-band for improved signal-to-noise ratio (SNR). The proposed approach tackles the drawback of the previous active noise shaping (increased power and extra noise) and passive noise shaping (limited noise suppression and signal loss). Both noise shaping and gain multiplication are realized on-chip in an energy-efficient manner without an opamp. This approach uses only capacitors and switches in the finite impulse response (FIR) and infinite impulse response (IIR) filters. A comparator suppressing kickback noise is presented to handle the tradeoff between noise suppression and the filter capacitor size. The energy-efficient merged-capacitor switching (MCS) technique is effectively combined with rail-to-rail swing comparator and thermometer-coded capacitor array, which reduces the settling error in the digital to analog converter (DAC). The process-induced mismatch effect in the capacitive DAC is investigated using a behavioral model of the ADC. Additionally, we propose dynamic element matching (DEM) for the thermometer-coded capacitor array. The ADC is fabricated using a 0.18 μm CMOS process in an area of 0.26 mm2. Consuming 4.1 μW, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 66.5 dB and a spurious-free dynamic range (SFDR) of 79.1 dB. The figure-of-merit (FoM) of the ADC is 11.8 fJ/conversion-step.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

Choi

Lee

2022

Sensors

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“…Recent researches had brought forward an attractive solution, the noise-shaping SAR (NS-SAR) ADC, which combines the oversampling and noise-shaping techniques with SAR ADC [14,15,16,17,18,19,20,21,22,23]. The active noise-shaping technique proposed in Refs.…”

Section: Introductionmentioning

confidence: 99%

“…Refs. [20,21,22,23] has designed several fullypassive switch capacitor integrators, mainly including Cascaded Integrator Feed-Forward (CIFF) and Error-Feedback (EF) structures. As shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique

Yang

Jiang

et al. 2020

IEICE Electron. Express

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This paper presents an optimized Fully-Passive Noise-Shaping Successive Approximation Register (FPNS-SAR) Analog-to-Digital Converter (ADC) with passive gain and integration capacitor reuse techniques. Instead of using multi-input-pair comparator with active gain in traditional Cascaded Integrator Feed-Forward (CIFF) structure, 1-input-pair comparator with passive gain is adopted in this paper to reduce power consumption and kick-back noise. The proposed FPNS-SAR ADC was implemented with standard 65-nm CMOS process. With the oversampling ratio (OSR) of 8, the simulation results realize 79.3 dB peak SNDR and 94 dB peak SFDR at 6.25 MHz input signal bandwidth and 100 MHz sampling frequency. The proposed ADC consumes 1.245 mW at 1.2 V supply voltage. The calculated FOMw and FOMs are 13.2 fJ/conv.-step and 176.3 dB, respectively.

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“…In recent years, there has been emerging efforts to try to enable the application of SAR ADCs to the regime of high‐resolution

normalΔ normalΣ

ADCs. The noise‐shaping SAR ADCs, which suppress the comparator and quantisation noise in the signal band, can achieve an effective number of bits (ENOB) of around 13 bit [1, 2]. However, further resolution improvement of SAR ADCs is limited by the non‐linearity caused by the DAC mismatch.…”

Section: Introductionmentioning

confidence: 99%

Second‐order DAC MES for SAR ADCs

Liu

Sun

2017

Electron. lett.

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The successive approximation register (SAR) ADCs suffer from capacitor mismatch when considered for high-precision applications. Recently, a mismatch error shaping (MES) technique suitable for SAR ADCs has been proposed, by which the DAC mismatch error is first-order highpass shaped. The MES technique to the secondorder is generalised. A concrete implementation of the second-order MES is presented. Theoretical analysis and simulations verify the feasibility and validity of the proposed technique. Compared to the previous one, the proposed second-order MES shows significantly improved shaping effect.

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A 13b-ENOB 173dB-FoM 2^nd-order NS SAR ADC with passive integrators

Cited by 42 publications

References 0 publications

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique

Second‐order DAC MES for SAR ADCs

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A 13b-ENOB 173dB-FoM 2nd-order NS SAR ADC with passive integrators

Cited by 42 publications

References 0 publications

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An 11.8-fJ/Conversion-Step Noise Shaping SAR ADC with Embedded Passive Gain for Energy-Efficient IoT Sensors

An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique

Second‐order DAC MES for SAR ADCs

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A 13b-ENOB 173dB-FoM 2^nd-order NS SAR ADC with passive integrators