An optimized fully-passive noise-shaping SAR ADC with integration capacitor reuse technique

Abstract

This paper presents an optimized Fully-Passive Noise-Shaping Successive Approximation Register (FPNS-SAR) Analog-to-Digital Converter (ADC) with passive gain and integration capacitor reuse techniques. Instead of using multi-input-pair comparator with active gain in traditional Cascaded Integrator Feed-Forward (CIFF) structure, 1-input-pair comparator with passive gain is adopted in this paper to reduce power consumption and kick-back noise. The proposed FPNS-SAR ADC was implemented with standard 65-nm CMOS process. With the oversampling ratio (OSR) of 8, the simulation results realize 79.3 dB peak SNDR and 94 dB peak SFDR at 6.25 MHz input signal bandwidth and 100 MHz sampling frequency. The proposed ADC consumes 1.245 mW at 1.2 V supply voltage. The calculated FOMw and FOMs are 13.2 fJ/conv.-step and 176.3 dB, respectively.

A 200kHz-bandwidth 101dB SNDR noise-shaping SAR ADC with NTF strengthening method

“…6. ISSCC 2019 [8] ISSCC 2020 [16] ISSCC 2021 [9] VLSI 2022 [5] IEICE 2020 [24] Harmonic distortion limits the SNDR of the ADC, as can be seen in Fig. 8, which shows the variation of SFDR with input signal frequency.…”

A 10.31 ENOB 3.125MHz BW fully passive 2nd-order noise-shaping SAR ADC for low cost IoT sensor networks

“…The dynamic amplifier doesn't consume static power, but its gain is sensitive to the PVT variation [14][15][16]. The fully passive noise-shaping scheme, which does not require an amplifier and only relies on the switching capacitor circuit, has the highest power efficiency [17][18][19][20][21]. However, the NTF of passive NS-SAR is hard to optimize due to the capacitor size limitation and the attenuation on the signal path.…”