A 14 b 40 MSample/s pipelined ADC with DFCA

Abstract

TX capacitor mismatch is a major factor limiting high-resolution AUCs. A number of traditional techniques to ovemme this limitation are outlined in Table 8.6.1, along with the proposcd DAC and feedback capacitor averaging (DFCA) technique and mismatch noise cancellation (MNC) technique.DFCA simultaneously shuffles both the DAC and the feedback capacitors, resulting in high SFDR. Figure 8.6.1 shows the overall ADC architecture for chip I (DFCA) and chip I1 (DFCA + MNCI. Stages 1-5 are 3b/stage, followed by stage 6, which is a 4b flash ADC. The choice of 3blstage is a tradeoff between power consumption, conversion speed, and circuit complexity. Shufiling is applied to stages 1-3. The resulting broadband noise from shuffling can be cancelled using MNC, employing CDMA-like concepts Ill. MNC differs from the DAC Noise Cancellation 1 2 1 in that both DAC and interstage gain errors are cancelled. To cancel the mismatch noise from stage 1, MNC takes the 1Zh error-correctod outputs from stages 2~6, estimates and eancols the capacitor mismatch in the background and combines with the raw 3h from stage 1 to produce the final 14b.In conventional dynamic element matching (DEM) techniques, themometer codes are shuffled in digital domain after the latches. When applied to a pipelined ADC, this implies an increase of the non-overlapping period of the clock, limiting the ADC conversion speed. Figure 8.6.2 shows tho DFCA implemented. Shufiling occurs in the analog domain before the latches. Theanan-overlapping time can therefore be reduced to accommodate only the simple capacitor switch logic (CSLI. Unlike DEM in U converters, where mismatch noise shaped spectrum limits the input signal bandwidth to a fraction of the Nyquist rate, DFCA achieves high SFDR while remaining compatihlc with broadband Nyquist-rate ADCs.In addition, DFCA removes interstage gain error due to capacitor mismatch, while XA DEM removes only DAC errors. DFCA-MNC comhination acts as background calibration by continuously canceling out capacitor mismatch. Previous background calibration techniques address only DAC errors 121 or interstage gain error 131, and can require extra analog components 141. The DFCA-MNC combination is free of these drawbacks.Each pipeline stage uses four capacitors on each side of the fully differential ADC. The stage is configured in the amplification phase in Figure 8.6.2a. Since the total number of capacitors including the feedback capacitor is a power of two, DFCA implementation is simple. At any given clock cycle, one of four capacitors is randomly selected as the feedback capacitor, while the remaining three DAC capacitors arc shumed simultaneously.In Figure 8.6.2h, one side of the fully differential parallel shuffling networks (PSN) is shown. The inputs to the shuffling networks are analog signals representing 2b codes alaO, blbO, clc0, and flm. Since the feedback capacitors arc shumed along with the DAC capacitors, the bottom plate of each capacitor can have one of four connections: VREF+, VCM, VREF~, and Vom of the opamp. The cod...

Functional simulation of a technique for background calibration of capacitor mismatch errors in pipelined A/D converters

“…P 1 , P 2 , and P 3 are zeromean, pseudo-random binary variables with values ±1 which define how the four physical capacitors C 1 , C 2 , C 3 , and C 4 are assigned to the role of C a , C b , C c , and C f . Shuffling alone improves the spurfree dynamic range of the converter [4] at the expense of an increase of the noise floor. This extra noise, however, can be used to estimate and correct the MDAC errors.…”

“…7c reports the results obtained when the exact correction formula (1) is used; Fig. 7d shows the results obtained according to [5], using approximation (4).…”

“…Background calibration of DAC and interstage gain errors can be accomplished by one of the techniques recently reported in the literature [2][3][4][5]. A pseudo-random perturbation is introduced in the DAC operation, and the residue, quantised by the ADCs of the following stages, is correlated with the perturbation so as to identify and correct the effects of non-ideal weighting.…”

“…Different architectures for the introduction of the random perturbation are at the heart of the various techniques. Among them, [4,5] address the calibration of gain and capacitor mismatch errors in a capacitive DAC-subtractor, directly driven by the thermometer code output of a flash ADC stage.…”

“…This paper first shows that, for a given resolution of the complete A/D converter, there is an upper bound to the mismatch error which can be corrected according to [4,5]. A different procedure is provided for the correction of the residue, which, unlike [5], does not require neglecting second order error terms.…”