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TX capacitor mismatch is a major factor limiting high-resolution AUCs. A number of traditional techniques to ovemme this limitation are outlined in Table 8.6.1, along with the proposcd DAC and feedback capacitor averaging (DFCA) technique and mismatch noise cancellation (MNC) technique.DFCA simultaneously shuffles both the DAC and the feedback capacitors, resulting in high SFDR. Figure 8.6.1 shows the overall ADC architecture for chip I (DFCA) and chip I1 (DFCA + MNCI. Stages 1-5 are 3b/stage, followed by stage 6, which is a 4b flash ADC. The choice of 3blstage is a tradeoff between power consumption, conversion speed, and circuit complexity. Shufiling is applied to stages 1-3. The resulting broadband noise from shuffling can be cancelled using MNC, employing CDMA-like concepts Ill. MNC differs from the DAC Noise Cancellation 1 2 1 in that both DAC and interstage gain errors are cancelled. To cancel the mismatch noise from stage 1, MNC takes the 1Zh error-correctod outputs from stages 2~6, estimates and eancols the capacitor mismatch in the background and combines with the raw 3h from stage 1 to produce the final 14b.In conventional dynamic element matching (DEM) techniques, themometer codes are shuffled in digital domain after the latches. When applied to a pipelined ADC, this implies an increase of the non-overlapping period of the clock, limiting the ADC conversion speed. Figure 8.6.2 shows tho DFCA implemented. Shufiling occurs in the analog domain before the latches. Theanan-overlapping time can therefore be reduced to accommodate only the simple capacitor switch logic (CSLI. Unlike DEM in U converters, where mismatch noise shaped spectrum limits the input signal bandwidth to a fraction of the Nyquist rate, DFCA achieves high SFDR while remaining compatihlc with broadband Nyquist-rate ADCs.In addition, DFCA removes interstage gain error due to capacitor mismatch, while XA DEM removes only DAC errors. DFCA-MNC comhination acts as background calibration by continuously canceling out capacitor mismatch. Previous background calibration techniques address only DAC errors 121 or interstage gain error 131, and can require extra analog components 141. The DFCA-MNC combination is free of these drawbacks.Each pipeline stage uses four capacitors on each side of the fully differential ADC. The stage is configured in the amplification phase in Figure 8.6.2a. Since the total number of capacitors including the feedback capacitor is a power of two, DFCA implementation is simple. At any given clock cycle, one of four capacitors is randomly selected as the feedback capacitor, while the remaining three DAC capacitors arc shumed simultaneously.In Figure 8.6.2h, one side of the fully differential parallel shuffling networks (PSN) is shown. The inputs to the shuffling networks are analog signals representing 2b codes alaO, blbO, clc0, and flm. Since the feedback capacitors arc shumed along with the DAC capacitors, the bottom plate of each capacitor can have one of four connections: VREF+, VCM, VREF~, and Vom of the opamp. The cod...

An engineering reasoning has been followed to design an LMS algorithm with power-of-two quantized error for tracking a plant whose parameters vary according to a random walk. Design equations of the quantizer saturation level, number of quantizer bits, and algorithm step size have been provided. A practically useful conclusion of the note is that no significant improvement of the algorithm performance will be obtained by using more than three bits for the quantizer when tracking a random walk channel. REFERENCESS. H. Cho and V. J. Mathews, "Tracking analysis of the sign algorithm in nonstationary environments," design of signed regressor LMS algorithm for stationary and nonstationary adaptive filtering with correlated Gaussian data," ZEEE Trans. Abstract-A simple pipelined A/D conversion technique, which providessuperior monotonicity to that of conventional pipelined converters is presented. The technique involves simple re-arrangement of the feedback capacitor. Unlike existing techniques, it does not add circuit complexity, increase power consumption, or sacrifice conversion speed. On the contrary, the technique allows the use of smaller capacitors for a given differential linearity target, thereby reducing the power consumption while maintaining the speed. The technique is applicable to pipelined architectures with a wide range of bits per stage including 1-b/stage. Monte Carlo simulation indicates that at 3-0 levels, 0.781% capacitor mismatch combined with 1.56%-of-full-scale comparator errors provides over 95.2% 12-b yield in a 2-b/stage architecture.Abstract-A new circuit configuration is presented, which takes advantage of the normally unused counterpropagating output of a distributed amplifier. The feasibility is demonstrated by a matched filter circuit with dual gate FET's for a 700 Mb/s NRZ signal. Modifications are proposed to extend this technique to a more general case of signal shaping.