A pipelined A/D conversion technique with near-inherent monotonicity

Yu, P.C.; Lee, Hae-Seung

doi:10.1109/82.401178

Cited by 23 publications

(6 citation statements)

References 5 publications

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“…7(c). It is shown in [30] that this operation gives the characteristic in Fig. 8 despite capacitor mismatches.…”

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 85%

“…The converter characteristic in Fig. 8 can be obtained by the commutative feedback capacitor switching (CFCS) in [30]. CFCS is implemented by slightly altering the basic operation of the standard converter shown in Fig.…”

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 99%

“…Alternating between these two characteristics at the sampling rate pushes the mismatch error to high frequencies. In addition to the reduced differential nonlinearity (DNL) [30], the 1-bit-per stage CFCS ADC has a transfer characteristic with a nonlinear portion which is even. That is, the integral nonlinearity (INL) is even.…”

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 99%

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Oversampled pipeline A/D converters with mismatch shaping

Shabra

Lee

2002

IEEE J. Solid-State Circuits

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This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADC's transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-m CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level.

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“…7(c). It is shown in [30] that this operation gives the characteristic in Fig. 8 despite capacitor mismatches.…”

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 85%

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 99%

Section: Mismatch Shaping Using the Cfcs Pipeline Adcmentioning

confidence: 99%

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Oversampled pipeline A/D converters with mismatch shaping

Shabra

Lee

2002

IEEE J. Solid-State Circuits

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“…In [10] another correction technique which allows a compact implementation, is introduced. Just like our new approach, it does not require a calibration cycle.…”

Section: Introductionmentioning

confidence: 99%

A digital error-averaging technique for pipelined A/D conversion

Rombouts

Weyten²

1998

IEEE Trans. Circuits Syst. II

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1321[10], "Deterministic analysis of 61 modulation for linear and nonlinear signal reconstruction," Int. Abstract-Capacitor mismatch is the main source of nonlinearity for pipelined analog-to-digital (A/D) converters. Here a digital erroraveraging technique is presented to greatly reduce this effect. Compared to the conventional circuit, the new approach requires only one extra digital addition. This allows a very simple and compact implementation.On the other hand, the conversion speed is halved because one conversion now requires two clock cycles instead of one. Therefore this technique is most suitable when moderately high speed combined with high resolution is required.

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“…The reference feedforward technique [66] and commutated feedback capacitor switching (CFCS) [67,68] improve the DNL, but do not affect the INL. In 1-bit/stage architecture the capacitive error averaging technique, which has previously been used in algorithmic ADCs [69], can be used [70,71].…”

Section: Switched Capacitor Realizationmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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A pipelined A/D conversion technique with near-inherent monotonicity

Cited by 23 publications

References 5 publications

Oversampled pipeline A/D converters with mismatch shaping

Oversampled pipeline A/D converters with mismatch shaping

A digital error-averaging technique for pipelined A/D conversion

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

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