A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC

A novel swapping technique for stage nonlinear error calibration in Pipeline ADCs (analogue-todigital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-toanalogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.

Section: Swapping Calibration Methodsmentioning

confidence: 97%

Section: Calibration Algorithmmentioning

confidence: 94%

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

Ginés

Peralías

Rueda

2008

“…Also, the time-interleaving architecture [7,8] could not show a good dynamic performance due to the mismatches between the time-interleaving channels and usually needs complex calibration scheme to correct the mismatches [9]. The opamp sharing architecture only needs half the number of opamps thereby could reduce significant power consumption [10][11][12][13].…”

Section: Adc Architecturementioning

confidence: 99%

Design of an ADC for subsampling video applications

Zeng

Zhang

et al. 2006

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for highspeed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-ofmerit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable highswing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-µm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm 2 .

“…Thus, a single comparator, set of current sources, and feedback capacitor are shared between two MDACs alternately. This is akin to the opamp and capacitor sharing [16][17][18], and produces a further reduction in power consumption and chip area.…”

Section: Introductionmentioning

confidence: 99%

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

Woo

Kim

2014

In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 lm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power.