A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR &gt; 70 dB up to 1.2 GHz

Zuo, Zhiheng; Fan, Qingjun; Chen, Jinghong

doi:10.1109/iscas.2017.8050688

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A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz

Cited by 4 publications

References 8 publications

A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS Technology

A Low-Power 10-Bit 2GS/s Hybrid Time-Interleaved Digital-to-Analog Converter with a New Neutrolized-Glitch Unit Current Cell in 65 nm CMOS Technology

Implement of a 10-bit 7.49 mW 1.2GS/s DAC with a new segmentation method

Static Digital Pre-Distortion Method for High-Speed Current-Steering Digital-to-Analog Converters

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