A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

Ali, Ahmed; Dinc, Huseyin; Bhoraskar, Paritosh; Puckett, Scott; Morgan, Andy; Zhu, Ning; Yu, Qin; Dillon, Chris; Gray, Bryce; Lanford, Jon; McShea, Matt; Mehta, Ushma; Bardsley, Scott; Derounian, Peter; Bunch, Ryan; Moore, Ralph; Taylor, Gerry

doi:10.1109/vlsic.2016.7573537

Cited by 47 publications

(17 citation statements)

References 3 publications

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“…9, whereas Fig. 10 shows results for 500 random BW mismatches (see (28)) and I/Q time skews (see (29)) uniformly distributed in the interval…”

Section: Simulation Results the Performance Of The Proposed Backpropa...mentioning

confidence: 99%

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On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Solis,

Reyes,

Morero

et al. 2020

Preprint

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This paper introduces a backpropagation-based technique for the calibration of the mismatch errors of timeinterleaved analog to digital converters (TI-ADCs). This technique is applicable to digital receivers such as those used in coherent optical communications. The error at the slicer of the receiver is processed using a modified version of the well known backpropagation algorithm from machine learning. The processed slicer error can be directly applied to compensate the TI-ADC mismatch errors with an adaptive equalizer, or it can be used to digitally estimate and correct said mismatch errors using analog techniques such as delay cells and programmable gain amplifiers (PGA). The main advantages of the technique proposed here compared to prior art are its robustness, its speed of convergence, and the fact that it always works in background mode, independently of the oversampling factor and the properties of the input signal, as long as the receiver converges. Moreover, this technique enables the joint compensation of impairments not addressed by traditional TI-ADC calibration techniques, such as I/Q skew in quadrature modulation receivers. Simulations are presented to demonstrate the effectiveness of the technique, and low complexity implementation options are discussed.

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“…9, whereas Fig. 10 shows results for 500 random BW mismatches (see (28)) and I/Q time skews (see (29)) uniformly distributed in the interval…”

Section: Simulation Results the Performance Of The Proposed Backpropa...mentioning

confidence: 99%

“…Dither injection techniques are based on the addition of a signal in either the analog or digital domain to facilitate the estimation of the calibration parameters [25], [28], [29], [36]. They are often used in high resolution ADCs (> 10 effective number of bits or ENOB).…”

Section: Introductionmentioning

confidence: 99%

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Solis,

Reyes,

Morero

et al. 2020

Preprint

View full text Add to dashboard Cite

show abstract

“…Nowadays, in the designs of high speed and high resolution pipeline ADC [4,5,6,7,8,9,10,11], low open-loop gain interstage residue amplifiers (RAs) are gradually replacing the traditional high gain amplifiers, mainly including the following two reasons: 1) as the technology scales down, both the supply voltage and inherent gain of transistors are decreasing, which make the design of high gain amplifiers more difficult, 2) low gain amplifiers can achieve lower power consumption and noise.…”

Section: Introductionmentioning

confidence: 99%

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

Ding

Miao

et al. 2022

IEICE Electron. Express

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This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-todigital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40 nm CMOS technology , similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74 dB and 43.61 dB to 70.54 dB and 89.8 dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.

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“…Ultra high-speed analog-to-digital converters (ADCs) are playing critical roles in software defined radios, optical communications and high-end test equipment [1,2,3]. With the continuous development of digital process, the demand for high performance ADCs in multi-GHz range becomes more and more urgent.…”

Section: Introductionmentioning

confidence: 99%

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS

Liu

Zhou

et al. 2019

IEICE Electron. Express

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In this paper, a time-interleaved 10-GS/s 8-bit analog-to-digital converter (ADC) fabricated in 0.18 µm SiGe BiCMOS technology has been demonstrated. A 4 × 4 input multiplexer with good isolation and wide input bandwidth is proposed, which enables the ADC to support 1/2/4-channel sampling modes. In the track-and-hold (THA) stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the overshoot effect of the SEF output. The ADC achieves spurious free dynamic range (SFDR) > 52 dBc and effective number of bits (ENOB) > 6.8 in low input frequencies. The analog input bandwidth is 5.6 GHz.

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A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

Cited by 47 publications

References 3 publications

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS

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