On the Application of Error Backpropagation to the Background Calibration of Time Interleaved ADC for Digital Communication Receivers

Solis, Fredy; Reyes, Benjamín T.; Morero, Damián A.; Hueda, Mario R.

doi:10.48550/arxiv.2008.02914

Cited by 1 publication

(1 citation statement)

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“…m,p E{E k } can be replaced by a noisy estimation ∇ g (i) m E k , as usual with the SGD based adaptation. As we show in the Appendix of [49], an instantaneous gradient of the squared error ( 17) can be expressed as…”

Section: Error Backpropagationmentioning

confidence: 99%

Error-Backpropagation-Based Background Calibration of TI-ADC for Adaptively Equalized Digital Communication Receivers

Solis¹,

Reyes²,

Morero

et al. 2022

IEEE Access

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A novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) is presented in this paper. This technique is applicable to equalized digital communication receivers. As shown in the literature, in a digital receiver it is possible to treat the TI-ADC errors as part of the communication channel and take advantage of the adaptive equalizer to compensate them. Therefore calibration becomes an integral part of channel equalization. No special purpose analog or digital calibration blocks or algorithms are required. However, there is a large class of receivers where the equalization technique cannot be directly applied because other signal processing blocks are located between the TI-ADC and the equalizer. The technique presented here generalizes earlier works to this class of receivers. The error backpropagation algorithm, traditionally used in machine learning, is applied to the error computed at the receiver slicer and used to adapt an auxiliary equalizer adjacent to the TI-ADC, called the Compensation Equalizer (CE). Simulations using a dual polarization optical coherent receiver model demonstrate accurate and robust mismatch compensation across different application scenarios. Several Quadrature Amplitude Modulation (QAM) schemes are tested in simulations and experimentally. Measurements on an emulation platform which includes an 8 bit, 4 GS/s TI-ADC prototype chip fabricated in 130nm CMOS technology, show an almost ideal mitigation of the impact of the mismatches on the receiver performance when 64-QAM and 256-QAM schemes are tested. INDEX TERMS Background calibration, error backpropagation, optical coherent receiver, TI-ADC, TI-ADC mismatch calibration. I. INTRODUCTION T HIS paper proposes a novel background calibration technique for Time-Interleaved Analog-to-Digital Converters (TI-ADCs) used in equalized digital communication receivers. It generalizes a previously proposed technique [1]-[3]. Current and emerging digital receivers for ultra highspeed communication systems [4]-[10] require large bandwidth, high sampling rate ADCs. Please see [11] and references therein for a recent review of interleaving techniques for high speed data converters. The TI-ADC has been the technique predominantly used to meet the demanding sampling rate and bandwidth requirements of high-speed transceivers [12], [13]. The per-formance of TI-ADCs is affected by mismatches among the interleaves [14], [15]. Mismatches of sampling time, gain, bandwidth, as well as DC offset, are the most common impairments. Many calibration techniques have been proposed in the literature. Please see [16]-[41] and references therein for a thorough review and discussion. Calibration techniques for general purpose TI-ADCs in general require dedicated calibration blocks and algorithms. On the other hand, several authors [1]-[3] have shown that in the special case of an equalized digital receiver, it is possible to treat the TI-ADC errors as integral part of the communication channel and take advantage of the already ex...

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Section: Error Backpropagationmentioning

confidence: 99%