A 14-bit 500-MS/s DAC with 211-MHz 70 dB SFDR bandwidth using TRI-DEMRZ

Lai, Longqiang; Li, Xueqing; Liu, Jianan; Yang, Huazhong

doi:10.1007/s10470-018-1141-5

Cited by 6 publications

(2 citation statements)

References 32 publications

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“…Then input data changed with the generated value and the barrel shifter gives out the corresponding output. The complexity of proposed DEM is equivalent to conventional RRBS and simpler than most of existing DEMs used for reducing glitch [26,27,28]. For every 3-bit part, it needs 3-bit code to generate rotation number like the 6-bit DAC designed in the section 2.…”

Section: Simulated Resultsmentioning

confidence: 99%

A glitch energy reduction method with low complexity dynamic element matching for data converters

Liu

Zhang

et al. 2023

IEICE Electron. Express

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Due to the appearance of huge glitch while using traditional Dynamic Element Matching (DEM) in data converters, different kinds of glitch-reduce structures are designed into DEM. However, most of these structures will work with high complexity. Based on random-rotationbinary-weighted selection (RRBS), this paper presents a novel low complexity glitch-reduced DEM algorithm, which can greatly reduce mismatch. The proposed DEM constructs glitch-reduce structure through data selector and comparator, so the complexity is reduced through using less components. As a result, the glitch-reduced DEM increases spurious free dynamic range (SFDR) to 92.47dB at 7.6MHz. Moreover, compared with conventional RRBS, glitch-reduced DEM makes the glitch reduce by 49% with low complexity in a 12-bit digital-to-analog converter (DAC).

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Section: Simulated Resultsmentioning

confidence: 99%

A glitch energy reduction method with low complexity dynamic element matching for data converters

Liu

Zhang

et al. 2023

IEICE Electron. Express

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“…The glitch generates nonlinearity and affects the DAC output, thereby degrading SFDR performance. One of the drawbacks of using the DEM technique is the switching glitch [16], [18], [25]. Although the previous work on the DEM technique have resolved the glitch problem, the additional complex logics proposed in the previous studies may not be suitable for low power sensor node applications.…”

Section: B Designing a Prototype 12-bit Dac Using Lw-demmentioning

confidence: 99%

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

Yoon

Jung

et al. 2019

IEEE Access

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The need for low-power wireless sensor networks (WSNs) continues to grow. Based on the fact that digital-to-analog converters (DACs) are essential elements in the WSN and consumes a lot of power, this paper presents a new low-power DAC design to realize the low-power WSN. To do that, this paper exploits the dynamic element matching (DEM) technique, one of the well-known techniques for high performance DACs, proposes a lightweight DEM (LW-DEM) technique that minimizes power and area overhead of the DEM technique. More specifically, this paper is motivated from the observation that input data of DACs tends to be sufficiently random that the input data can be used for the random selection of the current source instead of a pseudo-random number generator (PRNG) for the traditional DEM. Because the PRNG consumes a lot of power and occupies a large area in a DAC, elimination of the PRNG from a DAC and utilizing input data result in significant power saving and area reduction in the DAC while meeting the required performance of the low-power WSNs. This paper provides a detailed LW-DEM architecture and its operation principle. To demonstrate the efficacy of the proposed method, a prototype 12-bit DAC using the LW-DEM is implemented. The 12-bit DAC is fabricated in 65 nm CMOS technology and occupies only 0.065 mm 2 area. Measurement results with the prototype verify that the DAC using LW-DEM accomplishes 39% power saving and 52% area reduction in the randomizer, compared to a DAC using the conventional DEM. At the same time, the measured spurious-free dynamic range (SFDR) of the DAC using LW-DEM is better than 55 dB, demonstrating that the proposed DAC achieves almost same performance as a DAC using the conventional DEM.

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An on-chip partial self-healing calibration technique for 10-bit reused distributed current steering DAC

Samanta

Sarkar²

2022

Analog Integr Circ Sig Process

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A 14-bit 500-MS/s DAC with 211-MHz 70 dB SFDR bandwidth using TRI-DEMRZ

Cited by 6 publications

References 32 publications

A glitch energy reduction method with low complexity dynamic element matching for data converters

A glitch energy reduction method with low complexity dynamic element matching for data converters

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique

An on-chip partial self-healing calibration technique for 10-bit reused distributed current steering DAC

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