A 14-bit High Speed 125MS/s Low Power SAR ADC using Dual Split Capacitor DAC Architecture in 90nm CMOS Technology

Abstract

The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81 dB, and an effective-number-of-bits (ENOB) of 13.16 bits with a sampling rate of 125MS/s.

Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

“…Where the charge injection is defned as the charge that exists between the source and drain terminals when the sample switch is turned of, and the clock feed through is defned as the charge injected due to the overlapping coupling capacitor between the gate and drain terminals. Consequently, it is preferable to implement the sample switch by using CMOS transmission gates [8,64,103] or the bootstrap switch in Figure 4 [2,5,6,11,17,22,24,31,34,45,53,58,63,65 Te variations in conductivity are reduced by utilizing the CMOS transmission gates, but the problem of input dependence still exists. Additionally, a large parasitic capacitor that limits the resolution of SAR appears.…”

“…Comparator. Te preamplifer stage, single-stage dynamic latch, and bufer stage are integrated in the SAR comparator [1,31,103] to decrease the delay, power consumption, kick-back noise, and the inputreferred ofset voltage. Also, two inverter stages may be used with the single-stage dynamic latch [29,52,58] to avoid the static current at the reset phase and to enhance the driving capability and achieve rail-to-rail digital output.…”

“…Te widespread adoption of DAC in distinct biomedical applications today has elevated the need for power consumption reduction [31]. Te purpose of the DAC is straightforward.…”

“…Meanwhile, to decrease the die size, cost, and the threshold voltage, the MIM (metal-isolated-metal) capacitor DAC array is replaced by a MOS capacitor [29]. Also, a modifed two-stage dual split CDAC array technique is used to avoid the mismatch ofset and reduce the capacitor array size [31][32][33][34]. Tis structure may be divided into three stages: subarray capacitor, the MSB, MLSB and LSB as shown in Figure 11.…”

“…While in the nonredundant SAR logic [4,31,64,92], the number of registers has shrunk to less than half the sequence/code structure. Tis structure depends on the state of each bit and the previous bits' state, as indicated in Figure 37.…”