A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Abstract

Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

“…Negative bitline (NBL) scheme, Wordline overdrive (WLOD) scheme, Lowering cell V DD voltage (V DDCELL ) (LCV) scheme [2] and Raising cell ground voltage (V SSCELL ) (RCGV) scheme. Figure 1(a) shows the schematic of an 6T SRAM bitcell and Fig.…”

“…Also, this technique shows highest WM without reducing the ADM of the half selected bitcells [2]. To realize NBL write assist scheme, capacitive coupling signal (CCS) approach shown in Fig.…”

“…Further WLUD scheme also shows rise in access time of bitcell with reducing V MIN , then to improve the V MIN , disturbance noise reduction (DNR) scheme was proposed as read assist scheme [2]. In this scheme, both the bitlines are lowered simultaneously, before the WL is activated to reduce the level of noise injection to the bitcell nodes, by discharging through clamping and discharge blocks.…”

“…The reduction in V MIN of the SRAM cell for scaled devices is limited because of the local threshold voltage variations resulting from random dopant fluctuations and lithographic-dependent patterns have been increasing [1]. Also, with the increased threshold voltage variations in scaled transistors the access-disturbance margin (ADM) [2] and write margin (WM) [3] of the SRAM bitcell have been degrading. Process variations make SRAM design less predictable and controllable, moreover the SRAM design space in terms of prediction and control degrades further as supply voltage (V DD ) scales down [5].…”

“…These schemes use higher supply voltage for bitcell array and lower supply voltage for peripheral blocks to improve the ADM of an SRAM. Write margin (WM) of an SRAM bitcell, has been improved by pushing selected bitline to negative voltage or by decreasing the cell voltage [2]. Now a days SRAM read and write assist techniques are widely used approaches to lower the V MIN of an SRAM [8].…”