A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

Palmer, R.; Poulton, John W.; Dally, William J.; Eyles, John; Fuller, Andrew M.; Greer, Thomas H.; Horowitz, Mark; Kellam, M.; Quan, F.; Zarkeshvari, F.

doi:10.1109/isscc.2007.373483

Cited by 44 publications

(18 citation statements)

References 3 publications

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“…Our target external memory bandwidth for a 10 teraflop processor is 10 TB/s. Using an electrical interconnect to achieve this performance would require excessive power; over 160 W assuming 2 mW/Gb/s [25] interconnect power. Instead, we use a nanophotonic interconnect that has high bandwidth and low power.…”

Section: Optically Connected Memorymentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

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We expect that many-core microprocessors will push performance per chip from the 10 gigaflop to the 10 teraflop range in the coming decade. To support this increased performance, memory and inter-core bandwidths will also have to scale by orders of magnitude. Pin limitations, the energy cost of electrical signaling, and the non-scalability of chip-length global wires are significant bandwidth impediments. Recent developments in silicon nanophotonic technology have the potential to meet these off-and on-stack bandwidth requirements at acceptable power levels.Corona is a 3D many-core architecture that uses nanophotonic communication for both inter-core communication and off-stack communication to memory or I/O devices. Its peak floating-point performance is 10 teraflops. Dense wavelength division multiplexed optically connected memory modules provide 10 terabyte per second memory bandwidth. A photonic crossbar fully interconnects its 256 low-power multithreaded cores at 20 terabyte per second bandwidth. We have simulated a 1024 thread Corona system running synthetic benchmarks and scaled versions of the SPLASH-2 benchmark suite. We believe that in comparison with an electrically-connected many-core alternative that uses the same on-stack interconnect power, Corona can provide 2 to 6 times more performance on many memoryintensive workloads, while simultaneously reducing power.

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Section: Optically Connected Memorymentioning

confidence: 99%

Corona: System Implications of Emerging Nanophotonic Technology

Vantrease

Schreiber

Monchiero

et al. 2008

2008 International Symposium on Computer Architecture

429

479

View full text Add to dashboard Cite

show abstract

“…For longer reach interconnections that suffer from losses due to high-frequency attenuation, it may be possible to utilize low signal swing to reduce power [38], but ultimately, channel quality limits the practicality of such techniques as transceiver circuits can dominate total power. Recent work on low-power serial links has focused on equalization techniques [39]- [41], which may benefit somewhat from the general CMOS voltage scaling strategies described in this paper; however, voltage scaling in analog circuits may be limited and parallelism is likely not a viable solution in this case.…”

Section: E Off-chip Connectionsmentioning

confidence: 99%

Practical Strategies for Power-Efficient Computing Technologies

et al. 2010

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| After decades of continuous scaling, further advancement of silicon microelectronics across the entire spectrum of computing applications is today limited by power dissipation. While the trade-off between power and performance is well-recognized, most recent studies focus on the extreme ends of this balance. By concentrating instead on an intermediate range, an $ 8Â improvement in power efficiency can be attained without system performance loss in parallelizable applicationsVthose in which such efficiency is most critical. It is argued that power-efficient hardware is fundamentally limited by voltage scaling, which can be achieved only by blurring the boundaries between devices, circuits, and systems and cannot be realized by addressing any one area alone. By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified. Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system. The IBM Blue Gene system is then presented as a case study to exemplify several proposed directions. Going forward, further power reduction may demand radical changes in device technologies and computer architecture; hence, a few such promising methods are briefly considered.

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“…Recently a number of low power SR-SERDES have been demonstrated [25,10]. In switch applications, "long reach" or LR-SERDES are generally required so as to drive a path of up to one meter of PC board trace with at least two backplane connectors in the path.…”

Section: Electrical I/o Roadmapmentioning

confidence: 99%

“…Historical data show that SERDES power scales by roughly 20% per year [25]. Not all components of SERDES power will continue to scale at this rate.…”

Section: Electrical I/o Roadmapmentioning

confidence: 99%

The role of optics in future high radix switch design

Binkert

Davis

Jouppi

et al. 2011

Proceedings of the 38th Annual International Symposium on Computer Architecture

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For large-scale networks, high-radix switches reduce hop and switch count, which decreases latency and power. The ITRS projections for signal-pin count and per-pin bandwidth are nearly flat over the next decade, so increased radix in electronic switches will come at the cost of less per-port bandwidth. Silicon nanophotonic technology provides a long-term solution to this problem. We first compare the use of photonic I/O against an all-electrical, Cray YARC inspired baseline. We compare the power and performance of switches of radix 64, 100, and 144 in the 45, 32, and 22 nm technology steps. In addition with the greater off-chip bandwidth enabled by photonics, the high power of electrical components inside the switch becomes a problem beyond radix 64.We propose an optical switch architecture that exploits highspeed optical interconnects to build a flat crossbar with multiplewriter, single-reader links. Unlike YARC, which uses small buffers at various stages, the proposed design buffers only at input and output ports. This simplifies the design and enables large buffers, capable of handling ethernet-size packets. To mitigate head-of-line blocking and maximize switch throughput, we use an arbitration scheme that allows each port to make eight requests and use two grants. The bandwidth of the optical crossbar is also doubled to to provide a 2x internal speedup. Since optical interconnects have high static power, we show that it is critical to balance the use of optical and electrical components to get the best energy efficiency. Overall, the adoption of photonic I/O allows 100,000 port networks to be constructed with less than one third the power of equivalent all-electronic networks. A further 50% reduction in power can be achieved by using photonics within the switch components. Our best optical design performs similarly to YARC for small packets while consuming less than half the power, and handles 80% more load for large message traffic.

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A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications

Cited by 44 publications

References 3 publications

Corona: System Implications of Emerging Nanophotonic Technology

Corona: System Implications of Emerging Nanophotonic Technology

Practical Strategies for Power-Efficient Computing Technologies

The role of optics in future high radix switch design

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