A 15 ns 32&amp;amp;amp;times;32-bit CMOS multiplier with an improved parallel structure

Nagamatsu, M.; Tanaka, S.; Mori, J.; Noguchi, T.; Hatanaka, K.

doi:10.1109/cicc.1989.56842

Cited by 15 publications

(5 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, using larger counters to build PPRT is not beneficial. The introduction of 4:2 compressor was a departure from the counter-based scheme [7], [8], [9]. As the delay paths are well balanced, the latency for a 4:2 compressor is only three XOR delays, rather than two full adder delays.…”

Section: Introductionmentioning

confidence: 99%

“…Note that, when applying associative property to combine the multiplexing operations, one should not violate the noncommute property. For example, r iYn and g iYn will be incorrect if (r iÀIYn , g iÀIYn ) and (r jYm , g jYm ) are exchanged in (7) and (8). Based on the above two observations and using the equations from (4) to (10), we developed our MLCSMA algorithm.…”

mentioning

confidence: 99%

“…The carry signal PT arrives at t = 10 and the inputs PT , PU , PT , and PU arrive at t = 7.5. Because the timing difference is sufficiently large to span another level of CCA, the program constructs a 2-bit CCA section and generates r HYPU and g HYPU by using ( 7) and (8). Similarly, 2-bit CCA sections are constructed for the successive 6 bits.…”

mentioning

confidence: 99%

“…Similarly, 2-bit CCA sections are constructed for the successive 6 bits. However, since the timing difference of r HYQI and r HYQQ is smaller than one unit delay, both the level spanned at n = 31 and the level spanned at n = 33 are terminated and combined to form r IYQQ and g IYQQ by using (7) and (8). By repeating these steps, QQ is produced at t = 11.…”

mentioning

confidence: 99%

See 3 more Smart Citations

High-speed Booth encoded parallel multiplier design

Yeh

Jen

2000

IEEE Trans. Comput.

196

View full text Add to dashboard Cite

ÐThis paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.

show abstract

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

mentioning

confidence: 99%

See 2 more Smart Citations

High-speed Booth encoded parallel multiplier design

Yeh

Jen

2000

IEEE Trans. Comput.

196

View full text Add to dashboard Cite

show abstract

“…In some cases, to achieve better regularity for integration, a 4-to-2 compressor [101] might be built from 2 CSAs as in figure 5.7 and used for the compressor tree. However, this would slightly increase the number of levels in the tree, although the speed of these compressors can be optimized [62]. Higher order compressors may be built [66], such as a 9-to-2 compressor described in [81]; the best solution to reduce the partial products is to optimize the entire compressor tree [67,84].…”

Section: Mul/div Functional Unit Implementationmentioning

confidence: 99%

Adding limited reconfigurability to superscalar processors

Epalza

Ienne²,

Mlynek

Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004.

View full text Add to dashboard Cite

For the last thirty years, electronics, at first built with discrete components, and then as Integrated Circuits (IC), have brought diverse and lasting improvements to our quality of life. Examples might include digital calculators, automotive and airplane control assistance, almost all electrical household appliances, and the almost ubiquitous Personal Computer. ApplicationSpecific Integrated Circuits (ASICs) were traditionally used for their high performance and low manufacturing cost, and were designed specifically for a single application with large volumes. But as lower product lifetimes and the pressures of fast marketing increased, ASICs' high design cost pushed for their replacement by Microprocessors. These processors, capable of implementing any functionality through a change in software, are thus often called General Purpose Processors.General purpose processors are used for everyday computing tasks, and found in all personal computers. They are also often used as building blocks for scientific supercomputers. Superscalar processors such as these require ever more processing power to run complex simulations, video games or versatile telecoms services. In the case of embedded applications, e.g. for portable devices, both performance and power consumption must be taken into account.In a bid to adapt a processor to some extent to select applications, fully reconfigurable logic can greatly improve the performance of a processor, since it is shaped for the best possible execution with the available resources. However, as reconfigurable logic is far slower than custom logic, this gain is possible only for some specific applications with large parallelism, after a detailed study of the algorithm. Even though this process can be automated, it still requires large computing resources, and cannot be performed at run time.To reduce the loss in speed compared to custom logic, it is possible to limit the reconfigurability to increase the breadth of applications where performance can be improved. However, as the application space increases, a careful analysis and design of the reconfigurability is required to minimize the speed loss, notably when dynamic reconfiguration is considered.iii iv As a case study, we analyze the feasibility of adding limited reconfigurability to the Floating Point Units (FPUs) of a general purpose processor. These rather large units execute all floating point operations, and may also be used for integer multiplication. If an application contains few or infrequent instructions that must be executed by the FPU, this idle hardware only increases power consumption without enhancing performance. This is often the case in non-scientific applications and even many recent and detailed video games which make heavy use of hardware display accelerators for 3D graphics.In a fast multiplier such as can be found in the FPU of a high performance processor, the logic to perform multiplication is a large tree of compressors to add all the partial products together. It is possible to add logic to a...

show abstract

VLSI CMOS Subsystem Design

Bellaouar

Elmasry

1995

Low-Power Digital VLSI Design

View full text Add to dashboard Cite

A 15 ns 32&amp;times;32-bit CMOS multiplier with an improved parallel structure

Cited by 15 publications

References 5 publications

High-speed Booth encoded parallel multiplier design

High-speed Booth encoded parallel multiplier design

Adding limited reconfigurability to superscalar processors

VLSI CMOS Subsystem Design

Contact Info

Product

Resources

About