A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC

In this paper a dual operating mode 8-bit, 1.1-V pipeline ADC for Gigabit Ethernet applications is presented. In the two operating modes, the ADC features different sampling frequency (125 and 250 MHz) and power consumption (9.4 and 22.8 mW). Considering a signal bandwidth of 60 MHz in both operating modes, as required by the Gigabit Ethernet standard, the ADC achieves a SNDR always larger than 39.4 dB at 125 MHz and 38.7 dB at 250 MHz (6.25-bit and 6.13-bit ENOB, respectively), with a FoM of 0.84 pJ/conv at 125 MHz and 2.2 pJ/conv at 250 MHz. The ENOB achieved is mainly limited by clock jitter. The ADC is fabricated with a 90-nm CMOS technology, with an active area of 1.25 9 0.65 mm 2 .

Section: Resultsmentioning

confidence: 83%

“…Most of the solutions presented in literature use the first approach [2,3]. In this paper, a versatile ADC that can be used in both cases is proposed [4].…”

Section: Introductionmentioning

confidence: 99%

A 90-nm CMOS, 8-bit pipeline ADC with 60-MHz bandwidth and 125-MS/s or 250-MS/s sampling frequency

Malcovati

Picolli

Crespi

et al. 2009

“…However, the pseudo differential architecture [6] could not provide a good dynamic performance for the relatively high frequency inputs due to its non-differential nature and hence the higher evenorder harmonics compared with that of the fully differential one. Also, the time-interleaving architecture [7,8] could not show a good dynamic performance due to the mismatches between the time-interleaving channels and usually needs complex calibration scheme to correct the mismatches [9]. The opamp sharing architecture only needs half the number of opamps thereby could reduce significant power consumption [10][11][12][13].…”

Section: Adc Architecturementioning

confidence: 99%

“…Hence, dynamic latch-type comparators [8] without any preamplifier to cancel the offset voltage are used in order to reduce the power consumption of the ADC. The ADC also includes an on-chip precision bandgap reference voltage generator and buffer amplifiers to generate positive, negative reference voltages for the MDACs.…”

Section: Other Componentsmentioning

confidence: 99%

Design of an ADC for subsampling video applications

Zeng

Zhang

et al. 2006

This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for highspeed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-ofmerit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable highswing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-µm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm 2 .

“…Recently, a lot of low-power technologies are proposed and verified in several designs. However, the time-interleaving architecture [1,2] is easily limited by offset and gain mismatches as well as aperture errors between the interleaved channels. The performance of the pseudo-differential architecture [3] compared with that of the fully differential one, is sensitive to the common mode voltage and substrate or power supply noise.…”

Section: Introductionmentioning

confidence: 99%

A 1.8-V 11-bit 40-MS/s 21-mW pipelined ADC

Fan

Ren

et al. 2010

A set of low-power techniques is proposed to realize low power design in pipeline analog-to-digital converter (ADC). These techniques include removing the active S/H (i.e., SHA-less), sharing the opamp between the adjacent multi-bit-per-stages, low-power high-efficiency high-swing amplifier technique. Also, a new sampling topology is proposed to minimize aperture error by matching the time constant between the two input signal paths. All these skills are verified by simulation in the design of the 1.8-V 11-bit 40-MHz ADC in a 0.18-lm CMOS process with power dissipation 21-mW, signal-tonoise-and-distortion ratio (SNDR) 65-dB, effective number of bit (ENOB) 10.5-bit, spurious free dynamic range (SFDR) 78-dB, total harmonic distortion (THD) -75.4-dB, signal-to-noise ratio (SNR) 65.4-dB and figure-of-merit (FOM) 0.18 pJ/step.