A 16-bit 1 MSPS SAR ADC with foreground calibration and residual voltage shift strategy

Abstract

In this paper, a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter (SAR ADC) is developed by the CMOS 0.25 μm process. An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC. The SAR ADC has a chip area of 2.7 × 2.4 mm2, and consumes only 100 μW at the 2.5 V supply voltage with 100 KSPS. The INL and DNL are both less than 0.5 LSB.

A 16-bit 18-MSPS flash-assisted SAR ADC with hybrid synchronous and asynchronous control logic

“…The introduction of the floating inverter amplifier (FIA) enables lower comparator noise performance with reduced consumption [21] , whereas the FIA's performance is prone to process, voltage, and temperature (PVT) variations. The idea of kT/C noise cancellation allows for sampling with relatively small capacitance, thereby improving the energy efficiency of the ADC [17,22] . However, extra amplifiers are required to support the function of the kT/C noise cancellation.…”