A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98% using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converterC DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm 2 • It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

In this paper, a 16-bit 1MSPS foreground calibration successive approximation register analog-to-digital converter (SAR ADC) is developed by the CMOS 0.25 μm process. An on-chip all-digital foreground weights calibration technique integrating self-calibration weight measurement with PN port auto-balance technique is designed to improve the performance and lower the costs of the developed SAR ADC. The SAR ADC has a chip area of 2.7 × 2.4 mm2, and consumes only 100 μW at the 2.5 V supply voltage with 100 KSPS. The INL and DNL are both less than 0.5 LSB.

This paper presents a novel current mode differential UWB LNA. A common-gate stage with transformer realizes a low noise input matching and produces a current gain. The output of the LNA is differential current, which can avoid the current-to-voltage conversion. The LNA is simulated with TSMC 0.18 µm RF CMOS process. Simulation results show that the max noise figure is only 2.65 dB, transconductance gain is larger than 18.7 dB, input reflection coefficient is lower than 9:9 dB, and third order input intercept point is about 2.8 dBm over 3-5 GHz. With a voltage of 0.8 V, the power consumption is 11 mW. A comparison with conventional UWB LNA shows that this LNA has advantages of low voltage, low noise, high gain, and high linearity.