A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

Devarajan, S.; Singer, L.; Kelly, D.; Decker, S.; Kamath, Anant S.; Wilkins, Paul

doi:10.1109/jssc.2009.2032636

Cited by 101 publications

(34 citation statements)

References 19 publications

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“…[1]. However, the first stage of opamp adopts nMOS inputs in this design with a telescopic and gain-boosting structure in order to offer larger g m and higher gain.…”

Section: Resultsmentioning

confidence: 99%

“…Firstly, as the SHA-less structure is utilized in the proposed ADC, the sampling networks for sub-ADC and MDAC should closely match to minimize aperture error and a careful layout is essential as well. The second point is that the sampled capacitor should be discharged before next sampling for the purpose of eliminating nonlinear kickback [1]. Besides, a large clock jitter will affect high-frequency performance dramatically, so the differential clock input is introduced to remove common-mode noise.…”

Section: The Proposed14-bit Pipelined Adcmentioning

confidence: 99%

“…Because loc_res is irrelevant to PN [1], the parameter PN_modulate can be treated as a noise which can be removed by a low-pass filter. And the simplest digital lowpass filter is an accumulator that averages a large quantity of samples.…”

Section: The Implementation Of Calibration Algorithmmentioning

confidence: 99%

“…Recently, with the improvement of modern process technology, research on high-speed highresolution ADCs for communication systems has become one of the trends. These types of ADCs need to have an accuracy of over 14 bits and sample rate of over 100 MHz [1,2] and the pipelined ADCs are an acceptable architecture due to its characteristics [3]. Additionally, standard CMOS process has the advantages of lower cost and power consumption over expensive BiCMOS technology.…”

Section: Introductionmentioning

confidence: 99%

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A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Wang¹,

Fan²,

Pan³

et al. 2015

IEICE Electron. Express

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In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .

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“…[1]. However, the first stage of opamp adopts nMOS inputs in this design with a telescopic and gain-boosting structure in order to offer larger g m and higher gain.…”

Section: Resultsmentioning

confidence: 99%

Section: The Proposed14-bit Pipelined Adcmentioning

confidence: 99%

Section: The Implementation Of Calibration Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Wang¹,

Fan²,

Pan³

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…Other applications such as cable modems, CCD medical imaging, and computed tomography scanners have similar quantization requirements [3], [5], [6]. Among various ADC architectures, the pipelined ADC is considered as one of the best candidates to fulfil the above mentioned applications due to its power efficiency in realizing 12-16 bits resolution, 70-80 dB SNR, and 85-95 dB SFDR at a sampling range of 100-300 MS/s [7], [8].…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

Ginés

Peralías

Aledo

et al. 2019

Circuit Theory & Apps

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Summary This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

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A 16-bit, 125 MS/s, 385 mW, 78.7 dB SNR CMOS Pipeline ADC

Cited by 101 publications

References 19 publications

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

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