A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

Ali, Ahmed; Morgan, Andy; Dillon, Chris; Patterson, Greg; Puckett, Scott; Bhoraskar, Paritosh; Dinc, Huseyin; Hensley, Mike; Stop, Russell; Bardsley, Scott; Lattimore, D; Bray, Jeffery P.; Speir, Carroll; Sneed, R.

doi:10.1109/jssc.2010.2073194

Cited by 128 publications

(31 citation statements)

References 15 publications

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“…The ADC of Ref. [2] shows good performance, but it costs a large area and power consumption with complicated Summing Node Sampling (SNS) algorithm. In Ref.…”

Section: Resultsmentioning

confidence: 99%

“…Recently, with the improvement of modern process technology, research on high-speed highresolution ADCs for communication systems has become one of the trends. These types of ADCs need to have an accuracy of over 14 bits and sample rate of over 100 MHz [1,2] and the pipelined ADCs are an acceptable architecture due to its characteristics [3]. Additionally, standard CMOS process has the advantages of lower cost and power consumption over expensive BiCMOS technology.…”

Section: Introductionmentioning

confidence: 99%

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A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Wang¹,

Fan²,

Pan³

et al. 2015

IEICE Electron. Express

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In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spuriousfree dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm 2 .

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“…The ADC of Ref. [2] shows good performance, but it costs a large area and power consumption with complicated Summing Node Sampling (SNS) algorithm. In Ref.…”

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Wang¹,

Fan²,

Pan³

et al. 2015

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

“…As the analog front-end of the ADC, the S/H circuit needs to acquire a wideband input signal of high precision without introducing too much noise [9], [10]. As depicted in Fig.…”

Section: S/h Parasitic Optimizationmentioning

confidence: 99%

“…The main challenge of IF-sampling ADC is the linearity distortion at high input frequencies [9], [10], characterized by SFDR, which is of great importance for wireless communication systems since weak signals are supposed to be detected in the presence of strong nearby interferences. Therefore, a high SFDR is needed to mitigate the inter-modulation.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Zheng

Wang

et al. 2016

IEEE Trans. Circuits Syst. I

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Abstract-This paper presents a 14-bit 250 MS/s ADC fabricated in a 180 nm CMOS process, which aims at optimizing its linearity, operating speed, and power efficiency. The implemented ADC employs an improved SHA with parasitic optimized bootstrapped switches to achieve high sampling linearity over a wide input frequency range. It also explores a dedicated foreground calibration to correct the capacitor mismatches and the gain error of residue amplifier, where a novel configuration scheme with little cost for analog front-end is developed. Moreover, a partial non-overlapping clock scheme associated with a highspeed reference buffer and fast comparators is proposed to maximize the residue settling time. The implemented ADC is measured under different input frequencies with a sampling rate of 250 MS/s and it consumes 300 mW from a 1.8 V supply. For 30 MHz input, the measured SFDR and SNDR of the ADC is 94.7 dB and 68.5 dB, which can remain over 84.3 dB and 65.4 dB for up to 400 MHz. The measured DNL and INL after calibration are optimized to 0.15 LSB and 1.00 LSB, respectively, while the Walden FOM at Nyquist frequency is 0.57 pJ/step.

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“…Generally for low resolution ADCs (<10 bit) Walden's FoM [16](1-1) is used, while higher resolution ADCs, which are more often thermal noise limited, use a modification of Schreier's FoM [17] which also takes distortion into account [18](1-2). The main difference between the used FoMs is if energy scales with a factor of two per extra effective bit, or with a factor of four.…”

Section: Power Consumption and Areamentioning

confidence: 99%

Time-interleaved high speed D/A converters

Olieman¹

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A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

Cited by 128 publications

References 15 publications

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Time-interleaved high speed D/A converters

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