Digest of Technical Papers., Symposium on VLSI Circuits.
DOI: 10.1109/vlsic.1995.520686
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A 16 bit low-power-consumption digital signal processor using a 80 MOPS redundant binary MAC

H. Kabuo
1
,
Michio Okamoto
2
,
Ryuta Tanaka
3
et al.
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Cited by 3 publications
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An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Kabuo
1
,
Okamoto
2
,
Tanaka
3
et al. 1996
IEEE J. Solid-State Circuits
14
0
4
0
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An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor

Kabuo
1
,
Okamoto
2
,
Tanaka
3
et al. 1996
IEEE J. Solid-State Circuits
14
0
4
0
View full textAdd to dashboardCite

A 1.8 V 36 mW DSP for the half-rate speech codec

Shiraishi
1
,
Kawamoto
2
,
Ishikawa
3
et al.
Proceedings of Custom Integrated Circuits Conference
8
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1
0
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A 16 bit low-power-consumption digital signal processor for portable terminals

Ishikawa
1
,
Suzuki
2
,
Taki
3
et al.
Proceedings of ICUPC '95 - 4th IEEE International Conference on Universal Personal Communications
2
0
1
0
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