A 16-Mb MRAM featuring bootstrapped write drivers

Gogl, D.; Arndt, Christine; Barwin, J.; Bette, Ann-Christin; DeBrosse, J.; Gow, E.; Hoenigschmid, H.; Lammers, S.; Lamorey, M.; Long, Yu; Maffitt, T.; Maloney, Kenneth M.; Obermaier, W.; Sturm, A.; Viehmann, H.; Willmott, D.; Wood, Mark A.; Gallagher, W. J.; Mueller, Georg; Sitaram, A. R.

doi:10.1109/jssc.2004.842856

Cited by 43 publications

(16 citation statements)

References 3 publications

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“…2. Many improved solutions based on this architecture, such as the source degeneration scheme [12], body voltage biasing scheme [14], and split-path sensing scheme [15], etc. have also been presented.…”

Section: Conventional Sensing Circuits For Stt-mrammentioning

confidence: 99%

“…The sensing circuit generates a sensed data voltage (V data = V data0 or V data1 ) depending on the MTJ resistance state of the data cell (R mtj = R P or R AP ), and compares V data with a ref- [12]. Here, V ref is usually generated by a reference cell.…”

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confidence: 99%

“…However, low I read results in small sensing margin (SM) accordingly due to the relatively small TMR ratio (ß60%-200% at room temperature) of the present MTJ technology. Here, SM is defined as the average voltage difference between V data and V ref [12]- [14]. The RD and SM problems become even more serious with technology continuously scaling because of the reduced I C 0 , V dd , and the increased PVT variations.…”

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confidence: 99%

“…2. Schematic of the conventional sensing circuit for STT-MRAM with two sensing branches [12]. and disturbance-free (VTDF) sensing circuit to achieve this purpose by sacrificing the sensing time.…”

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confidence: 99%

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Variation-Tolerant and Disturbance-Free Sensing Circuit for Deep Nanometer STT-MRAM

Wang

Klein

et al. 2014

IEEE Trans. Nanotechnology

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This paper presents a high reliability sensing circuit for the deep nanometer spin-transfer torque magnetic randomaccess memory (STT-MRAM). This sensing circuit, using a triple-stage sensing operation and source follower charge transfer amplification, is able to tolerate mostly the process, voltage, and temperature variations, thus improving greatly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance. With the STMicroelectronics CMOS 40-nm design kit and a precise STT-MTJ compact model, Monte-Carlo simulations have been performed to evaluate its sensing reliability performance. Index Terms-(PVT) variations, read disturbance (RD), sensing circuit, sensing margin (SM), STT-MRAM.

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Section: Conventional Sensing Circuits For Stt-mrammentioning

confidence: 99%

mentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Variation-Tolerant and Disturbance-Free Sensing Circuit for Deep Nanometer STT-MRAM

Wang

Klein

et al. 2014

IEEE Trans. Nanotechnology

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“…MRAM as a fast and non-volatile memory with low-power consumption appears to be a suitable candidate for the next memory generation [3]. Due to process variations, such as etching, edge bound stress, ill-contact electrode, etc., the MTJs encounter certain damage.…”

Section: Introductionmentioning

confidence: 99%