Variation-Tolerant and Disturbance-Free Sensing Circuit for Deep Nanometer STT-MRAM

Wang, Kang; Li, Zheng; Klein, Jacques-Olivier; Chen, Yuanqing; Zhang, Youguang; Ravelosona, D.; Chappert, C.

doi:10.1109/tnano.2014.2357054

Cited by 53 publications

(17 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The main MRAM array architectures, e.g., 1T-1MTJ and cross-point, have been reported in [14,35,36]. In the classic 1T-1MTJ array (see Figure 3), MTJ locates in series with the access transistor, where gate is connected to the word-line (WL), drain to the bit-line (BL) crossing the MTJ and source to the source-line (SL).…”

Section: High Performance Mram Writingmentioning

confidence: 99%

“…In the classic 1T-1MTJ array (see Figure 3), MTJ locates in series with the access transistor, where gate is connected to the word-line (WL), drain to the bit-line (BL) crossing the MTJ and source to the source-line (SL). Once non-volatile data is stored the MRAM array, and a sense amplifier (e.g., pre-charge SA) is required for the read operation [35][36][37][38]. Other assisted blocks (e.g., write control circuit, voltage pulse controller in VCMA-MTJ) are needed as well.…”

Section: High Performance Mram Writingmentioning

confidence: 99%

“…With the continuous scaling of CMOS technology nodes, MRAM with design-for-reliability is required due to the impacts of parametric process variations, aging mechanisms and transient faults [35,36,[45][46][47][48]. In this section, the process variation, thermal variation and breakdown are reviewed for reliable MRAM design.…”

Section: Reliability Issuesmentioning

confidence: 99%

See 2 more Smart Citations

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Cai

Wang²,

Wang

et al. 2017

Applied Sciences

Self Cite

View full text Add to dashboard Cite

Featured Application: Non-volatile magnetic tunnel junction-based magnetoresistive random access memory as reliable, high energy efficiency Internet of Things (IoTs) node memory.Abstract: The Internet of Things (IoTs) relies on efficient node memories to process data among sensors, cloud and RF front-end. Both mainstream and emerging memories have been developed to achieve this energy efficiency target. Spin transfer torque magnetic tunnel junction (STT-MTJ)-based nonvolatile memory (NVM) has demonstrated great performance in terms of zero standby power, switching power efficiency, infinite endurance and high density. However, it still has a big performance gap; e.g., high dynamic write energy, large latency, yield and reliability. Recently, voltage-controlled magnetic anisotropy (VCMA) has been introduced to achieve improved energy-delay efficiency and robust non-volatile writing control with an electric field or a switching voltage. VCMA-MTJ-based MRAM could be a promising candidate in IoT node memory for high-performance, ultra-low power consumption targets.

show abstract

Section: High Performance Mram Writingmentioning

confidence: 99%

Section: High Performance Mram Writingmentioning

confidence: 99%

See 1 more Smart Citation

High Performance MRAM with Spin-Transfer-Torque and Voltage-Controlled Magnetic Anisotropy Effects

Cai

Wang²,

Wang

et al. 2017

Applied Sciences

Self Cite

View full text Add to dashboard Cite

show abstract

“…As the MTJ feature size scales down further, the read margin will get narrower and read reliability will become the new threat for STT-RAM cell [6]. Although a few publications have proposed many circuit design techniques to enhance the read reliability, such as [2], [9], they do not consider the temperature impact on read reliability and may not effectively reduce the read error rate within the whole working temperature range.…”

Section: Preliminaries and Related Workmentioning

confidence: 99%

A body-biasing of readout circuit for STT-RAM with improved thermal reliability

Yang

Cheng

Wang

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

Self Cite

View full text Add to dashboard Cite

International audienceAs the integration density rockets up for contemporary VLSI circuits, power consumption limits the scalability of technology advancement of CMOS. Spin transfer torque-magnetic random access memory (STT-MRAM), as one of the emerging non-CMOS technologies, has the promising prospect of low standby power, fast access speed and compatibility with the CMOS fabrication process. However, with the technology node scaling down, typical 1 Transistor-1 Magnetic Tunnel Junction (1T-1MTJ) STT-RAM cell suffers from severe reliability challenges, especially for read operation under temperature fluctuation. In this paper, we quantitatively analyze the temperature effect on read reliability of STT-RAM cell and propose a novel body-biasing feedback readout circuit design to improve the read sensing margin under different temperatures. The experiments based on 40nm CMOS technology and MTJ compact model validate the effectiveness of the proposed method. The improved sensing margin also permits a smaller sensing current for reading such that higher read energy efficiency can be achieved

show abstract

“…This resistance property allows MTJ to be compatible with CMOS sense amplifier circuit that detects the MTJ's configuration and amplifies them to logic level. Among various sense amplifiers [64][65][66], pre-charge sense amplifier (PCSA) is proposed to provide not only the best tradeoff between sensing reliability and power efficiency, but also high-speed performance [59]. Thereby we focus on PCSA and apply it for the hybrid logic circuits involved in this chapter.…”

Section: Sensing Circuitmentioning

confidence: 99%