A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing

Kasha, D.; Lee, W.L.; Thomsen, A.

doi:10.1109/4.772406

Cited by 25 publications

(10 citation statements)

References 6 publications

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“…Larger antialiasing resistors help isolate the external operational amplifiers from the transient effects of sampling, and thus improve overall system performance. The traditional input sampling structure can be made to have the same kT/C noise performance by sampling the input and the reference on both and [7]. However, it would still have the problem of signal-dependent current on the signal inputs.…”

Section: Modulator Designmentioning

confidence: 99%

A 16-bit 250-kHz delta-sigma modulator and decimation filter

Maulik

Chadha

Lee

et al. 2000

IEEE J. Solid-State Circuits

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This paper describes a delta-sigma analog-to-digital converter (ADC) capable of converting input frequencies up to 250 kHz. It consists of a fifth-order switched-capacitor delta-sigma modulator and a decimation filter. Various design optimizations in the modulator are presented. The decimation filter consists of a comb filter followed by a novel, highly efficient and scalable finite impulse response filter. The ADC was implemented in 0.6-m CMOS technology. It achieves a dynamic range of 94 dB.

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Section: Modulator Designmentioning

confidence: 99%

A 16-bit 250-kHz delta-sigma modulator and decimation filter

Maulik

Chadha

Lee

et al. 2000

IEEE J. Solid-State Circuits

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“…This paper presents a third-order single-loop single-bit delta-sigma modulator. The modulator uses opamp bias switching technique to reduce the power consumption by using high-order modulator [4]. The on-chip reference is placed on the same chip so that no sensitive analog connections are taken outside the package.…”

Section: Introductionmentioning

confidence: 99%

A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference

Kwak

Kim

Ahn

2012

2012 IEEE International Symposium on Circuits and Systems

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A switched-capacitor (SC) third-order single-loop single-bit delta-sigma analog-to-digital converter (ADC) for sensor interface is presented. The ADC is integrated on the same chip with a bandgap reference. To reduce the power consumption, opamp bias current switching technique is adopted. The prototype delta-sigma ADC fabricated in a 0.18μm CMOS process achieves 89.2 dB dynamic range (DR), 77.1 dB signal-to-noise ratio (SNR) and 77.0 dB signal-to-noise and distortion ratio (SNDR) over 10 kHz signal bandwidth with an over-sampling-ratio (OSR) of 128. The total power consumption is 1.42 mW at 1.8 V supply.

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“…A clocked current bias scheme for folded-cascade OP Amps suitable for achieving a wide dynamic range has typically been proposed to decrease the power consumption of the OP Amp itself [7,8]. Because the circuit requires complicated four-phase bias-current control pulses and biasing circuits, it results in a large layout area and is not suitable for the high-speed operation.…”

Section: Introductionmentioning

confidence: 99%

A Switched-Capacitor Low-Pass Filter with Dynamic Switching Bias OP Amplifiers

Wakaumi¹

2017

Adv. sci. technol. eng. syst. j.

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A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing

Cited by 25 publications

References 6 publications

A 16-bit 250-kHz delta-sigma modulator and decimation filter

A 16-bit 250-kHz delta-sigma modulator and decimation filter

A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference

A Switched-Capacitor Low-Pass Filter with Dynamic Switching Bias OP Amplifiers

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