A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

Reddy, Karthikeyan; Rao, Sachin; Inti, Rajesh; Young, Ben; Elshazly, Amr; Talegaonkar, Mrunmay; Hanumolu, Pavan Kumar

doi:10.1109/jssc.2012.2218062

Cited by 106 publications

(42 citation statements)

References 14 publications

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“…Based on these facts, shifting the quantization/conversion from the voltage domain to the time and/or digital domain is becoming increasingly attractive [5]- [12]. In Fig.…”

Section: Introductionmentioning

confidence: 99%

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A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

Xing

Gielen

2015

IEEE J. Solid-State Circuits

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A 40 MHz-BW 10 bit two-step VCO-based Delta-Sigma ADC is presented. With the open-loop structure and highly digital building blocks, a robust performance, high bandwidth and high power efficiency are achieved. The nonlinearities of the coarse and the fine VCO-based quantizers are mitigated by distortion cancellation and voltage swing reduction schemes respectively. Because of the intrinsic DEM of the VCO-based quantizer output, the matching requirement of the DAC cells is greatly relaxed. The experimental results in 40 nm CMOS show that, with 1.6 GHz sampling frequency, the proposed ADC reaches 59.5 dB SNDR and 67.7 dB SFDR for 40 MHz bandwidth. The power consumption is only 2.57 mW under 0.9 V power supply, corresponding the best FoM (42 fJ/step) among high bandwidth ( 20 MHz) DS ADCs.

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“…Based on these facts, shifting the quantization/conversion from the voltage domain to the time and/or digital domain is becoming increasingly attractive [5]- [12]. In Fig.…”

Section: Introductionmentioning

confidence: 99%

“…Because of the two-points nature of the PWM signal, the VCO oscillates at only two frequencies, being intrinsically linear. In [12], the VCO-based quantizer is only used for residual signal A/D conversion, and the VCO linearity is improved as its input voltage swing is reduced.…”

Section: Introductionmentioning

confidence: 99%

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

Xing

Gielen

2015

IEEE J. Solid-State Circuits

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“…However, the performance of VCO-based ADCs is severely limited by the inherent nonlinearity of the VCOs. Transistor-level simulations show that a dynamic range of about 40dB can be achieved at best in a straightforward VCO-based quantizer [3].…”

Section: Introductionmentioning

confidence: 99%

“…In [3], the VCO-based quantizer only processes the residual signal with limited input voltage swing and thus the nonlinearity is mitigated. In [4], the VCO operates at only two frequencies with the assistance of a pulse-width modulator (PWM) pre-driver and therefore is inherently linear.…”

Section: Introductionmentioning

confidence: 99%

A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

Zhu

Xing

Gielen

2014

ESSCIRC 2014 - 40th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB SNR/SNDR with a 40MHz bandwidth and consumes only 4.98mW. This corresponds to an excellent FoM of 35fJ/step.

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“…Pulse Width Modulation is a time domain modulation technique which is used in a wide variety of applications, such as time division multiplexing [1], optical data storage [2], power conversion [3]- [5], audio amplification [6] and control of VCO-Based ΔΣ ADCs [7]- [9]. The basic idea behind PWM is to embed the k th sample amplitude (b k ), of the continuous input signal into the width of the modulated signal in k th symbol interval.…”

Section: Introductionmentioning

confidence: 99%

I.I.D. stochastic analysis of PWM signals

Sevuktekin

Singer

2014

2014 48th Asilomar Conference on Signals, Systems and Computers

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A stochastic analysis for pulse width modulation (PWM) is given. Under a discrete random generator process with independent identically distributed (i.i.d.), continuous, rangelimited samples, stochastic models for different PWM signals are proposed. Using randomization of the signal starting point, wide sense stationarity (WSS) of proposed PWM signals are shown. Autocorrelation functions and their corresponding power spectrum densities (PSD) are derived in terms of the modified complementary cumulative distribution function of i.i.d samples. For the case where the samples are i.i.d. uniformly distributed, the proposed autocorrelation functions are tested with simulations.

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A 16-mW 78-dB SNDR 10-MHz BW CT $\Delta \Sigma$ ADC Using Residue-Cancelling VCO-Based Quantizer

Cited by 106 publications

References 14 publications

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS

A 40MHz-BW 35fJ/step-FoM nonlinearity-cancelling two-step ADC with dual-input VCO-based quantizer

I.I.D. stochastic analysis of PWM signals

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