A 16-Times Frequency Multiplier for 5G Synthesizer

Nam, Kyu‐Hyun; Hong, Nam-Pyo; Park, Jun‐Seok

doi:10.1109/tmtt.2021.3103203

Cited by 9 publications

(7 citation statements)

References 22 publications

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“…The simulation shows a timing jitter of 24 ps (pk-pk). A FOM (figure of merit) is derived from [15] to make a performance comparison with the state of the art. Equation (1) calculates the FOM using multiplication factor (N), Power Consumption (Pdc), Process minimum length (Lmin), operating bandwidth (BW in %), and Area (A).…”

Section: Resultsmentioning

confidence: 99%

“…The circuit utilizes a new simpler duty cycle correction loop offering multiplication of a wide frequency. The duty cycle correction loop also ensures minimal duty cycle distortion A FOM (figure of merit) is derived from [15] to make a performance comparison with the state of the art. Equation (1) calculates the FOM using multiplication factor (N), Power Consumption (Pdc), Process minimum length (L min ), operating bandwidth (BW in %), and Area (A).…”

Section: Discussionmentioning

confidence: 99%

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Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

Naveed,

Dix

2023

JLPEA

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A low-power delay-locked loop (DLL)-based frequency multiplier is presented. The multiplier is designed in 22 nm FDSOI and achieves 8× multiplication. The proposed DLL uses a new simple duty cycle correction circuit and is XOR logic-based for frequency multiplication. Current starved delay cells are used to make the circuit power efficient. The circuit uses three 2× stages instead of an edge combiner to achieve 8× multiplication, thus requiring far less power and chip area as compared to conventional phase-locked loop (PLL) circuits. The proposed 8× multiplier occupies an active area of 0.09 mm2. The measurement result shows ultra-low power consumption of 130 µW at 0.8 V supply. The post-layout simulation shows a timing jitter of 24 ps (pk-pk) at 2.44 GHz.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

Naveed,

Dix

2023

JLPEA

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“…For example, 𝑅 will be three times that of 𝑅 when H = 1.5, with a smaller current for the added negative-g m pair than the 𝐼 required to maintain the output amplitude. The negative-g m is able to improve the HRR performance [10]. Parallel RLC impedance, 𝑍 (𝜔), is expressed as…”

Section: Proposed 12-times Harmonic Generatormentioning

confidence: 99%

“…As shown in Fig. 6, we used the same cascode buffer topology in [10] to get more HRR and low power consumption, but we inserted a dc-blocking capacitor, C c , for better power optimization, as shown in Fig. 6.…”

Section: The Buffer With Constant Output Amplitude Controlmentioning

confidence: 99%

“…2(b)). An injection-locked frequency multiplier (ILFM) is able to suppress harmonics significantly by forcing oscillation at the desired harmonic, but it suffers from a limited injection-locking range, and additional error-correcting feedback circuitries are mostly required to secure a reliable operable frequency range [10]. A multi-phase-based topology (Fig.…”

Section: Introductionmentioning

confidence: 99%

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A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

Nam

Park

2022

J Electromagn Eng Sci

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This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time, τ , for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-gm differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm2, and power consumption is only 4 mW.

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Injection-Locked Frequency Sixtuplers in 90 nm CMOS by Using the Push-Push Doubler

Cheng,

Shen,

Hong

et al. 2023

IEEE Access

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This paper designs two single-stage LC-tank injection-locked frequency sixtuplers (ILFSs) fabricated in a 90 nm CMOS process and it describes the circuit design, operation principle, and measurement results of the ILFSs. The ILFS circuit with a differential input and single-phase output is made of a firstharmonic injection-locked oscillator (ILO), a frequency tripler, and a push-push doubler. The first ILFS uses an octagonal inductor. For a supply voltage of 0.4 V, the free-running frequency is around 41.52 GHz, DC power consumption is 9.03 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 10.21 %. The second ILFS uses an 8-shaped inductor for low electromagnetic (EM) noise generation. The free-running frequency is around 37.2 GHz, DC power consumption is 7.72 mW at the incident power of 0 dBm, and the output locking range at 0 dBm input power is 17.4 %. The two chips have the same area, 0.7 x 0.7 mm 2 . This paper also provides a further analysis and comparison of the RF performance of on-chip inductors designed. Simulation shows the substrate noise coupling and distance noise coupling between victim and aggressor, the 8-shaped inductor exhibits a significant reduction in coupling. By the measurement results, it is evident that the performance of the 8-shaped inductor ILFS is superior to that of the octagonal inductor ILFS.INDEX TERMS 5G, millimeter-wave (mm-wave), low power, LC-tank, gm-boosted, push-push frequency doubler, frequency tripler, 8-shaped inductor, injection-locked frequency sixtupler, locking range, 90nm CMOS, magnetic field coupling noise interference.

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A 16-Times Frequency Multiplier for 5G Synthesizer

Cited by 9 publications

References 22 publications

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

Design of a Low-Power Delay-Locked Loop-Based 8× Frequency Multiplier in 22 nm FDSOI

A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

Injection-Locked Frequency Sixtuplers in 90 nm CMOS by Using the Push-Push Doubler

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