A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Wu, Su-Hao; Kao, Tsung-Kai; Lee, Zwei-Mei; Chen, Ping; Tsai, Jui-Yuan

doi:10.1109/isscc.2016.7418016

Cited by 29 publications

(9 citation statements)

References 2 publications

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“…The complementary current-steering DAC, as shown in Fig. 10, is widely used in CT ADCs for its high power efficiency and low thermal noise [13], [28], [29]. Since the thermal noise and distortion of IDAC1 directly contribute to the output similar to the input signal, a supply of 1.5 V had to be used in IDAC1 to achieve sufficient voltage headroom for lower noise, while all other DACs are powered with a low supply of 1.1 V.…”

Section: Circuits Implementations a Dac Calibration Circuitsmentioning

confidence: 99%

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu

Xing

Gielen

2021

IEEE J. Solid-State Circuits

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This article presents a continuous-time (CT) analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a singleloop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoM S ) of 165.8 dB. Index Terms-2 b/cycle asynchronous successiveapproximation-register (ASAR), continuous-time (CT) analog-to-digital converter (ADC), flat signal transfer function (STF), noise-shaping (NS) QTZ, on-chip digital-to-analog converter (DAC) calibration, out-of-band blocker (OBB). I. INTRODUCTIONT HE ever more crowded radio spectrum causes great challenges to the design of wireless communication systems, in terms of increasing signal bandwidth (BW) as well as spectral performance. This makes continuous-time (CT) analog-to-digital converters (ADCs) more attractive for use in wireless applications due to their high dynamic range (DR), good power efficiency and implicit anti-aliasing property [1]-[3]. Fig. 1 shows the received spectrum at the antenna of the long-term-evolution advanced (LTE-A) standard [2], [4], [5]. For an inter-band contiguous carrier Manuscript

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Section: Circuits Implementations a Dac Calibration Circuitsmentioning

confidence: 99%

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Liu

Xing

Gielen

2021

IEEE J. Solid-State Circuits

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“…7(a), includes a primary unary element, I i , two auxiliary DACs, two registers to store the counter outputs and a mode-control logic that is used to configure the unit element in either normal or calibration mode depending on whether a calibration enable signal CAL is set to 0 or 1 respectively. In normal operation, the modecontrol block connects the 15-bit thermometer output code v [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] to the DAC inputs D [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15] while disabling the reference unit element, UE ref . With CAL set to 1, the modulator enters the calibration mode and all 15 primary elements are disconnected from the modulator feedback.…”

Section: Implementation Of Dac1 With Mode Controlmentioning

confidence: 99%

“…However, both schemes aggravate the linearity and bandwidth requirements of amplifiers in the loop filter. In [9], the ISI errors are adaptively compensated in background, but the technique requires high gain-bandwidth product (GBW) amplifiers for each unit element of the main DAC. Digital ISI shaping algorithms [10] are power-efficient alternatives, but they rely on high OSR and are not suitable for high-speed applications due to the added excess loop delay (ELD).…”

Section: Introductionmentioning

confidence: 99%

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

et al. 2019

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Calibration is preferred over dynamic element matching (DEM) techniques to correct nonlinearity in digital-to-analog converters (DACs) in high-speed multi-bit continuous-time (CT) delta-sigma modulators (DSMs) to avoid introducing extra excess loop delay. The state-of-the-art calibration techniques, however, involve substantial external control, making it difficult for a complete on-chip realization. In this paper a highly automated on-chip technique for calibrating differential nonlinearity (DNL) and inter-symbolinterference (ISI) errors of a multi-bit DAC in a CTDSM is presented. The proposed technique implements a Calibration Control System (CCS), equipped with a Finite State Machine (FSM) logic, that automates the entire calibration process with minimal intervention. The calibration loop utilizes the modulator itself to produce the digital estimates of the DNL and the average ISI errors of each unit element of the DAC. These digital estimates are then used to configure auxiliary DACs for correction of the errors in the main DAC. For every unit element in the main DAC, an 8-bit dynamic auxiliary DAC injects a calibrated compensation current in the loop at every up-transition of the input data to cancel the average ISI error, and a 5-bit constant current source array corrects its DNL error. Design considerations and post-layout simulation results for a 50-MHz bandwidth, 1.8GS/s 4 th -order CTDSM are presented. The modulator has a 4.8 dB and a 10.8 dB improvement in SNDR and SFDR respectively with calibration, leading to a dynamic range of 71 dB with a total power consumption of 37.7 mW from 1.3 V and 1 V supplies.INDEX TERMS Automatic on-chip DAC calibration, Gm-C based CTDSM, ISI compensation.

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“…However, the requirement of oversampling ratios (OSRs), which is typically over 16 [3][4][5][6] MHz BW have been proposed by using nanoscale CMOS processes, which allow multi-GHz clock rate. Previously, high frequency ADCs usually adopt continuous-time (CT) realizations [3][4][5][6][7][8][9] instead of discrete-time (DT) realizations. The latter is implemented by switched capacitor circuit, and its accuracy relies on capacitor matching, which means a robust operation under process variation is offered.…”

Section: Introductionmentioning

confidence: 99%

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

Xiao

Ren

et al. 2020

Nanoscale Res Lett

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The bandwidth of a modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.

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A 160MHz-BW 72dB-DR 40mW continuous-time ΔΣ modulator in 16nm CMOS with analog ISI-reduction technique

Cited by 29 publications

References 2 publications

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

An Automatic On-Chip Calibration Technique for Static and Dynamic DAC Error Correction in High-Speed Continuous-Time Delta-Sigma Modulators

A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

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