A 167-Processor Computational Platform in 65 nm CMOS

Truong, Dean N.; Cheng, W.H.; Mohsenin, Tinoosh; Yu, Zhou; Jacobson, Anthony T.; Landge, Gouri; Meeuwsen, M.J.; Watnik, C.; Tran, Anh; Xiao, Zhibin; Work, Eric; Webb, J.; Mejia, Paul; Baas, Bevan M.

doi:10.1109/jssc.2009.2013772

Cited by 168 publications

(61 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Assume fault rings (2, 2) and (3,5) exist in the center and the network is evaluated under synthetic traffic. Extended-XY [22] routing algorithm which can also support multiple fault rings is selected for fair comparison.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This is mainly due to traffic balance scheme adopted and the flexibility of setting routing restrictions introduced in Sect. 3.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Although the number of commercial processing cores is rather small, it is predicted to be doubled by each generation. Several representative works of NoCs are reported, like Tile64 TM from Tilera [1], 80-core Teraflops from Intel [2], and the 167-processor computational platform by UC Davis [3].…”

Section: Introductionmentioning

confidence: 99%

“…2D mesh topology is usually preferred for network-onchips (NoCs) design such as aforementioned work [1]- [3] due to its regularity and good layout and it is adopted in this work. For deep sub-micron (DSM) VLSI process, increasingly higher integration makes it difficult to guarantee cor- rect fabrication with an acceptable yield.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Shi

Zeng

2011

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

SUMMARYManufacturing defects in the deep sub-micron VLSI process and aging resulted problems of devices during lifecycle are inevitable, and fault-tolerant routing algorithms are important to provide the required communication for NoCs in spite of failures. The proposed algorithm, referred to as scalable and reconfigurable fault-tolerant distributed routing (RFDR), partitions the system into nine regions using the concept of divideand-conquer. It is a distributed algorithm, and each router guarantees faulttolerance within one's own region and the system can be still sustained with multiple fault areas. The proposed RFDR has excellent scalability with hardware cost keeping constant independent of system size. Also it is completely reconfigurable when new nodes fail. Simulations under various synthetic traffic patterns show its better performance compared to Extended-XY routing algorithm. Moreover, there is almost no hardware overhead compared to Logic-Based Distributed Routing (LBDR), but the fault-tolerance capacity is enhanced in the proposed algorithm. Hardware cost is reduced 37 % compared to Reconfigurable Distributed Scalable Predictable Interconnect Network (R-DSPIN) which only supports single fault region.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

“…This is mainly due to traffic balance scheme adopted and the flexibility of setting routing restrictions introduced in Sect. 3.…”

Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

Shi

Zeng

2011

IEICE Trans. Inf. & Syst.

Self Cite

View full text Add to dashboard Cite

show abstract

“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

Self Cite

View full text Add to dashboard Cite

Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

show abstract

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

Qian

Bai

Zhou

et al. 2017

IEEJ Transactions Elec Engng

View full text Add to dashboard Cite

Employment of fault‐tolerant techniques is necessary for the operability and reliability of very large scale integration (VLSI) arrays. Moreover, fault tolerance must be obtained at high speed on real‐time embedded systems. In this paper, a novel abstract model, based on the abstraction technique, is proposed to accelerate the reconfiguration of degradable VLSI arrays with low fault density. Given an m × n physical array with faults, the proposed technique extracts some physical rows including faulty elements to construct an abstraction array, ignoring the physical rows without faults, such that the size of original physical array can be significantly reduced to speed up the reconfiguration of VLSI array. In addition, we conclusively demonstrate the preservation of properties between the abstract array and the physical array to guarantee that the proposed technique is correct. Experimental results show that for a 128 × 128 physical array with 0.1% faults, a 15 × 128 abstract array can be constructed and the compression is more than 88.20%. This abstraction technique is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the running time can be improved by more than 66.79% for a 128 × 128 physical array with 0.1% faults. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

show abstract

A 167-Processor Computational Platform in 65 nm CMOS

Cited by 168 publications

References 19 publications

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

Contact Info

Product

Resources

About