A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate

Li, Yan; Lee, Seungpil; Fong, Y.; Pan, Feng; Kuo, Tien-Chien; Park, Jong; Samaddar, Tapan; Nguyen, Hao; Mui, Man; Htoo, Khin; Kamei, Takeshi; Higashitani, M.; Yero, E.; Kwon, Gyuwan; Kliza, P.; Wan, Ji; Kaneko, Tetsuya; Maejima, H.; Shiga, H.; Hamada, Makoto; Fujita, Norihiro; Kanebako, K.; Tarn, E.; Koh, A.; Kuo, C. P.; Pham, Trung; Huynh, Jonathan; Nguyen, Qui; Chibvongodze, Hardwell; Watanabe, Mitsuyuki; Oowada, K.; Grishma, Shah; Woo, B.J.; Ray, G. P.; Chan, Jennifer; Lan, J.; Patrick, Hong; Peng, Liping; Das, D.; Ghosh, D.; Kalluru, V.; Kulkarni, S.; Cernea, Raul; Huynh, Sharon; Pantelakis, D.; Wang, Chiming; Quader, K.

doi:10.1109/isscc.2008.4523279

Cited by 24 publications

(13 citation statements)

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“…Current EEPROM devices already store 4 bits (16 levels) in a single transistor of 100 × 100 nm area in 32 nm process (Li et al, 2008; Marotta et al, 2010). A good overview of EEPROM/Flash history was presented at ISSCC2012 (Harari, 2012).…”

Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.

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Section: Large-scale Neuromorphic Systemsmentioning

confidence: 99%

Finding a roadmap to achieve large neuromorphic hardware systems

2013

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“…The first X3 implementation had an 8-MBps write rate, which is comparable to the multilevel cell (MLC) write rate using HBL. 4 At the 2012 International Solid-State Circuits Conference, SanDisk reported on the development of a 128-Gbit X3 with 18-MBps write performance. 5 These additional improvements in X3 NAND flash write performance will reduce cost sufficiently to satisfy client applications.…”

Section: Architectural Improvementsmentioning

confidence: 99%

NAND Flash Memory: Challenges and Opportunities

Li¹,

Quader²

2013

Computer

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NAND flash offers a range of compelling benefits that will keep attracting mobile and enterprise application developers as engineers tackle the hard problems of scaling the technology to sub-20 nm.S ince NAND flash entered the market in 1987, its relatively low cost, compact size, quiet operation, speed, and ruggedness have made it a popular choice for mobile platforms such as smartphones and tablets, and it is replacing hard drives in many client and enterprise applications.In recent years, developers have successfully scaled 2D NAND flash to sub-20-nm technology, but further 2D NAND scalability will be a considerable challenge. Although new alternatives, such as 3D resistive RAM (ReRAM), are aiming to replace 2D NAND flash, NAND's entrenched position among nonvolatile storage options and the attractiveness of its low power consumption will make flash technology difficult to unseat. In enterprise storage, for example, flash solid-state drive (SSD) architectures are already leveraging massive parallelism to deliver high I/O operations per second for less power and cost than any currently available and practical technology.With these strong advantages, NAND can potentially supplant a portion of the dynamic RAM (DRAM) market, 1 and we expect future computing platforms to maximize NAND flash use in mobile, enterprise, and client product designs. Indeed, Gartner has forecast that units in all applications will triple over the next five years, with an average fourfold to fivefold capacity increase in SSDs over the same period. 2 The widespread adoption of flash will drive deeper cost reductions, which manufacturers will realize through increased scaling. As NAND flash devices scale down, application-specific systems management must maintain product reliability while continuing to address reduced endurance.Maintaining the reliability of NAND flash at 19 nm and beyond will also require breakthrough memory and system algorithms. Many efforts are in progress on more innovations in memory architecture, reliability, power, and high-speed I/O interfaces. Another body of work is focusing on the system design challenges of scaling 2D NAND flash, offering 3D NAND and other novel technologies as possible solutions. ArchitecturAl improvementsFor many years, half-bit-line (HBL), or shielded bit-line, architecture was the conventional NAND architecture in which, as Figure 1 shows, the system reads or writes only half the cells at a time to the word line. In 2008, SanDisk introduced all-bit-line (ABL) architecture, 3 which uses a current-sensing scheme to connect each bit line to the sensing amplifier and a set of data latches.ABL was a considerable improvement over HBL. In addition to doubling read and write throughput, ABL architecture has intrinsically better reliability. In HBL architecture, reading or programming stresses the same word line twice with high voltages; in ABL architecture, writing the same number of cells stresses the word line only once. The doubled high-voltage stress during program and read operations worsens m...

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“…Devices currently available use multiple levels and are referred to as multiple-level cell (MLC) flash. Four and eight levels are currently in use, and the number of levels will increase further to provide more storage capability [1] [2].…”

Section: Introductionmentioning

confidence: 99%

Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization

Wang

Courtade

Shankar

et al. 2011

2011 IEEE Global Telecommunications Conference - GLOBECOM 2011

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Abstract-High-capacity NAND flash memory can achieve high density storage by using multi-level cells (MLC) to store more than one bit per cell. Although this larger storage capacity is certainly beneficial, the increased density also increases the raw bit error rate (BER), making powerful error correction coding necessary. Traditional flash memories employ simple algebraic codes, such as BCH codes, that can correct a fixed, specified number of errors. This paper investigates the application of lowdensity parity-check (LDPC) codes which are well known for their ability to approach capacity in the AWGN channel. We obtain soft information for the LDPC decoder by performing multiple cell reads with distinct word-line voltages. The values of the word-line voltages (also called reference voltages) are optimized by maximizing the mutual information between the input and output of the multiple-read channel. Our results show that using this soft information in the LDPC decoder provides a significant benefit and enables the LDPC code to outperform a BCH code with comparable rate and block length over a range of block error rates.

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A 16Gb 3b/ Cell NAND Flash Memory in 56nm with 8MB/s Write Rate

Cited by 24 publications

References 1 publication

Finding a roadmap to achieve large neuromorphic hardware systems

Finding a roadmap to achieve large neuromorphic hardware systems

NAND Flash Memory: Challenges and Opportunities

Soft Information for LDPC Decoding in Flash: Mutual-Information Optimized Quantization

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