A 16Gbps Real-Time BF-based LDPC Decoder for IEEE 802.3an Standard

Abstract

Existing LDPC decoders are mostly based on belief-propagation (BP) algorithms for high decoding performance but demand high hardware cost, especially for applications with very high throughputs. In order to alleviate the problem, this work proposes a high-throughput LDPC decoder based on the much simpler bit-flipping (BF) algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is comparable to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.22M gates, 16Gbps and 315mW, respectively, at 500MHz clock rate.