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This paper proposes a novel systematic optimization long delay time and is always the critical path of the decoder. algorithm for comparison operations required by a check node unit Hence, [7] proposes a more efficient 6-input CNU architecture (CNU) in LDPC decoding, given any input number Nin. The to increase the speed of the whole decoder. However, those algorithm can automatically synthesize an optimized fast comparison operations that guarantees a shortest comparison delay time OfI ein r o pcfcly piie o h fiin comparison operations. To address this design challenge, this Flog (N -i)7 T and a minimized total number of two-input work is aimed to achieve the fastest comparison speed with comparators, where T is the delay time of a comparator. High lowest comparator complexity as much as possible.speed is achieved by adopting parallel divide-and-conquer 11. DECODING ALGORITHMS FOR LDPC CODES comparison operations, while the required comparators are minimized by developing a novel set construction algorithm that Decod maximizes shareable comparison operations. The designed CNU is ing of a LDPC code is generally carried out by Sumfavourable to the existing CNU designs which are non-systematically Product algorithm [8], which is based on log-likelihood ratio designed with either longer critical path delays or higher comparator (LLR) form of L(x) = log (P{x = O}/P{x = 1}) * In the ith counts than the proposed designs. The proposed design is particularly variable node vi, it needs to update the following message good for long code length cases, when it is impractical to do customized optimized designs by hand, due to high design LV , which will be sent by the variable node to check node complexity.

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