2008 2nd International Conference on Signal Processing and Communication Systems 2008

DOI: 10.1109/icspcs.2008.4813653

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An effective multibit-flipping algorithm for LDPC decoding

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Cited by 5 publications

References 9 publications

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A new simplified RRWBF decoding algorithm for LDPC decoder in CMMB

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2014

2014 7th International Congress on Image and Signal Processing

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A new simplified RRWBF decoding algorithm for LDPC decoder in CMMB

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2014

2014 7th International Congress on Image and Signal Processing

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A 16Gbps Real-Time BF-based LDPC Decoder for IEEE 802.3an Standard

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2011

2011 International Conference on Multimedia and Signal Processing

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Existing LDPC decoders are mostly based on belief-propagation (BP) algorithms for high decoding performance but demand high hardware cost, especially for applications with very high throughputs. In order to alleviate the problem, this work proposes a high-throughput LDPC decoder based on the much simpler bit-flipping (BF) algorithms, for the (2048, 1723) RS-LDPC code adopted in the IEEE 802.3an standard. High decoding performances and low iteration numbers are achieved by introducing a strategy of flipping low-correlation bits and an additional syndrome vote scheme. As a result, the decoding performance is comparable to the most popular BP-based min-sum algorithm (MSA) but with much lower computational complexity. Besides, the decoder achieves high hardware utilization with real-time processing capability. Synthesized with UMC 90nm process, the decoder chip area, throughput and average power dissipation are 1.22M gates, 16Gbps and 315mW, respectively, at 500MHz clock rate.

Error performance of LDPC decoder using bit flip algorithm

2016

2016 International Conference on Communication and Signal Processing (ICCSP)

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