A 16Hz–160kHz memristor emulator circuit

Sánchez–López, C.; Carrasco-Aguilar, M. A.; Muñiz-Montero, Carlos

doi:10.1016/j.aeue.2015.05.003

Cited by 110 publications

(40 citation statements)

References 20 publications

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“…It can be shown after considerable simplification that (8) and (9) have a pinch-off point [̂i n ,̂i n ] given bŷi…”

Section: Pinch Point Analysismentioning

confidence: 99%

“…The coefficients of the sin(⋅) and cos(⋅) terms in (8) and (9) are given in Table 1. Note that, with the exception of̂o ff , all coefficients in Table 1 are frequency dependent.…”

Section: The Proposed Circuitsmentioning

confidence: 99%

“…and the subscripts , refer to (8) and (9), respectively. The frequency dependent nature of (20) makes their analysis difficult; however, several observations can be deduced.…”

Section: Pinch Point Analysismentioning

confidence: 99%

“…Note that circuit realization of this model for the purpose of emulating its pinched hysteresis behavior in non-solid-state devices requires a multiplier block, an integrator block, and an adder [6]. Several other emulator circuits have recently been proposed in the literature [7][8][9][10][11][12][13]. It is important to note that (1) is nonlinear due to the multiplication term and that pinched hysteresis cannot appear in a linear system.…”

Section: Introductionmentioning

confidence: 99%

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CMOS Realization of All-Positive Pinched Hysteresis Loops

2017

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Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory. IntroductionPinched hysteresis was proposed to be a signature of memristive devices [1,2], yet it can also be observed in several other nonlinear devices such as nonlinear inductors (capacitors) with quadratic-type current (voltage) dependence [3]. Finding a general model for pinched hysteresis behavior was attempted in [4] for specific devices labeled as memristors [5]. In [6] and from a simplified mathematical point of view, the following model was proposed and shown to exhibit a pinched hysteresis behavior which can fit both chargecontrolled and flux-controlled memristance definitions:where if ( ) = V( ) and ( ) = ( ), the chargecontrolled memristance is obtained, while for the alternative setting ( ) = ( ) and ( ) = V( ), the flux-controlled memristance is obtained. In (1), the constants and are scaling and integration time constants, respectively. Note that circuit realization of this model for the purpose of emulating its pinched hysteresis behavior in non-solid-state devices requires a multiplier block, an integrator block, and an adder [6]. Several other emulator circuits have recently been proposed in the literature [7][8][9][10][11][12][13]. It is important to note that (1) is nonlinear due to the multiplication term and that pinched hysteresis cannot appear in a linear system. It is also possible to include other forms of nonlinearity that apply to the shaping of the loop as a result of shaping the applied excitation. This means replacing ( ) in (1) more generally with ( ( )). Pinched hysteresis loop is generally observed as a result of applying a bipolar sinusoidal voltage or current excitation signal and is thus symmetrical around the origin. Nonsymmetrical loops can also be obtained when the pinch point is shifted away from the origin. However, an all-positive pinched loop, to the best of our knowledge, has not been demonstrated before. It is the purpose of this work to introduce two simple circuits where this behavior is observed. We rely on the inherent nonlinearity of a MOS transistor to perform the multiplication operation required by (1) in order to obtain a charge-controlled memristance. Recall that a MOS transistor current-voltage relation can be described by

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“…It can be shown after considerable simplification that (8) and (9) have a pinch-off point [̂i n ,̂i n ] given bŷi…”

Section: Pinch Point Analysismentioning

confidence: 99%

“…The coefficients of the sin(⋅) and cos(⋅) terms in (8) and (9) are given in Table 1. Note that, with the exception of̂o ff , all coefficients in Table 1 are frequency dependent.…”

Section: The Proposed Circuitsmentioning

confidence: 99%

“…and the subscripts , refer to (8) and (9), respectively. The frequency dependent nature of (20) makes their analysis difficult; however, several observations can be deduced.…”

Section: Pinch Point Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

CMOS Realization of All-Positive Pinched Hysteresis Loops

2017

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“…Therefore, a replacement that behaves like a real memristor is still urgently needed to allow ordinary researchers to study memristor-based practical applications. Indeed, many memristor emulator circuits have been developed in recent years [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32]. For example, using a JFET to implement the required nonlinearity, a memristor emulator constructed with five operational amplifiers, a floating capacitor, a large number of resistors, and an analog multiplier is presented in [19].…”

Section: Introductionmentioning

confidence: 99%

A Novel Floating Memristor Emulator with Minimal Components

Zeng

2017

Active and Passive Electronic Components

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A new floating emulator for the flux-controlled memristor is introduced in this paper. The proposed emulator circuit is very simple and consists of only two current feedback operational amplifiers (CFOAs), two analog multipliers, three resistors, and two capacitors. The emulator can be configured as an incremental or decremental type memristor by using an additional switch. The mathematical model of the emulator is derived to characterize its behavior. The hysteresis behavior of the emulator is discussed in detail, showing that the pinched hysteresis loops in V-plane depend not only on the amplitude-to-frequency ratio of the exciting signal but also on the time constant of the emulator circuit itself. Experimental tests are provided to validate the emulator's workability.

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