A 170 mW 10 b 50 Msample/s CMOS ADC in 1 mm/sup 2/

Abstract

This 10b AD-converter at a sample rate of 50MSample/s, embedded in 50mnnz of digital circuitry, shows 8.7 effective bits. A straight flash-architecture would need 1023 accurate fast comparators. With a 2Vinput range, a comparator offset voltage of no more than lniV can be tolerated. Taking into account that the 1mV is a 3-6 sigma value, leads to a large chip. If, however, the signals to the comparator are amplified before the critical decision, simple small comparators would suffice. To cope with the dynamic offset caused by the clocking and latch action of the comparator itself, the architecture must tolerate comparator offsets of up to 60 -80mV. Hence, a gain of at least 30 is necessary. A single amplifier however, could not handle this, as the input range of 2V would be amplified to 60V. The approachhere is to use a distributed amplifier.An array of amplifiers is inserted between the input and the comparators. Each amplifier takes a reference voltage and the input signal, and amplifies the difference. If the input signal is not close to the reference voltage, the output is clipped. Although the large dynamic offset of the comparators is reducedin this way, the static offset of the amplifier stages remains.Reference 1 suggests averaging the output voltages of the individual amplifier stages by insertinglateral resistors between the outputs of neighboring stages. Each amplifier pulls its neighbors in the direction of its own decision, causing the final output voltages to be closer to the desired values. The lower the value of the lateral resistor, the more the improvement in accuracy. As reported in Rleference 1, however, inserting the lateral resistors decreases the gain of the stages, as it reduces the output impedance. In the optimum found in Reference 1, the DNL improved by about 1.5b. The approach here is to start with a high output impedance by usingcurrent source loads, instead ofresistors, and choosethe lakral resistor value as low as is possible, still yielding reasonable gain (4 to 5 times) (Figure la). The improvement in DNL obtained by this strategy (shown by the simulation results of Figure 2) is as much as 4b (24dB). All amplifiers are implemented as shown in Figure lb.In Figure 3a, the ladder and averagingresistors are shown as one continuous strip of resistive material. The linear input range of each amplifier stage is shown at the top of the diagram. When the input signal is centered around amplifier n, the current in the averaging resistor contains linear contributions from adjacent amplifiers as well. In this example, the linear input range overlaps 5 amplifiers. Therefore the rms offset voltage at stage n is reduced by d5. In general the offset (and therefore INL) after averaging is reduced by dN, where N is the number of amplifier stages operating in the linear input range at any one instant. The improvement in DNL is even larger because it is obtained by taking the difference oftwo output voltages, that after averaging, are highly correlated.Consider the stages n and n + l in Figure 3a. Eac...

A calibration-free 800MHz fractional-N digital PLL with embedded TDC

“…According to the Monte-Carlo simulations, DNL can be more than half LSB without the resistors. This technique resembles the resistor averaging approach used commonly in a flash ADC to alleviate the offsets of the pre-amplifiers [6].…”