A 174μVRMS Input Noise, 1 GS/s Comparator in 22nm FDSOI with a Dynamic-Bias Preamplifier Using Tail Charge Pump and Capacitive Neutralization Across the Latch

Abstract

Comparators are the core of analog-to-digital converters (ADC), used as sense amplifiers in on-chip data communication links and memories. The time taken by clocked comparator to resolve analog inputs near its input-referred noise level into digital output (called CLK-OUT delay, Fig. 1) often dictates system's throughput for a given SNR. For SAR ADCs where each bit is determined sequentially, CLK-OUT delay presents a bottleneck in realizing high speed operation e.g. beyond 100MS/s in 5G/6G baseband application. For 12-bit 100MS/s SAR ADC at 1V e.g. the comparator should resolve signals below 0.5mV within 500ps. Time-interleaving increases ADC throughput but at the cost of increased clock power. Therefore, low-noise energy-efficient GS/s comparators with sub-500ps CLK-OUT delay are indispensable not only for multi Gbps serial communication, but also in 5G/6G baseband ADCs. By eliminating static current, dynamic comparators (e.g. Elzakker [1], dynamic bias [2], inverter-amplifier [3]) perform comparisons with high energy-efficiency for a given noise level. However, the energyefficiency of these techniques [1-3] have been demonstrated only at low comparator speeds (below 100MS/s) with CLK-OUT delay in few ns [2] to tens of ns [3] range. Highspeed (GS/s) comparators [4][5][6][7] have been demonstrated at only medium noise level (few mVRMS) and are energy inefficient. This work presents an energy-efficient GS/s comparator targeting low-power and low-noise applications in high speed ADCs and serial communication. The proposed comparator's CLK-OUT delay and input referred noise remain well within 500ps and 0.5mVRMS over wide input common mode voltage, VCM (0.3-0.6V) while still maintaining <100fJ per comparison.

A 0.9 V high‐speed dynamic bias latch‐type comparator employing a voltage‐controlled delay line

“…The FoM of the proposed comparator (1.34) showcases a performance level comparable to the most energy‐efficient comparator [6] (FoM of 0.6 or 2) as detailed in Table 1. Additionally, the proposed comparator stands out as the fastest among other state‐of‐the‐art dynamic comparators [3–6] listed in Table 1.…”

“…Table 1 provides a comprehensive overview of the performance of this work and compares it with other state‐of‐the‐art dynamic comparators. The evaluation employs the figure‐of‐merit (FoM) as a benchmark, defined by the formula: FoM = (energy consumption per comparison) $$\times$$ $$\rm (\text{n}oise\; \text{v}oltage)^{2}$$$$\times$$(CLK‐OUT delay), where CLK‐OUT delay (comparison time) is measured for the input‐referred RMS noise level input voltage [6]. The FoM of the proposed comparator (1.34) showcases a performance level comparable to the most energy‐efficient comparator [6] (FoM of 0.6 or 2) as detailed in Table 1.…”

A 28 nm CMOS Triple-Latch Feed-Forward Dynamic Comparator With <27 ps / 1 V and <70 ps / 0.6 V Delay at 5 mV-Sensitivity

“…Table I summarizes the measured TLFF performance along with that of the SAC and the DTC on the same test-chip. Table II provides a state-of-the-art comparison of the proposed TLFF with the fastest deep-scaled CMOS comparators in literature, including a two-stage comparator [18], a 2×-interleaved single-stage SAC-like [19], a three-stage comparator with two pre-amplifiers [6], and a comparator with dynamic-bias pre-amplifier [20]. The introduced TLFF achieves the highest reported data rate of 13.5Gb/s with mV-range input sensitivity, while maintaining a BER below 10 -12 .…”

“…The input-referred noise of 0.89 mV rms and the energy/comparison of 163 fJ are on par with the stateof-the-art. The works in [6], [19], and [20] employ a very similar process feature size, while having the SOI advantage of reduced parasitics and better channel current control. Porting them to the 28nm bulk CMOS process at hand, and assuming a similar input-referred noise target, [6] is expected to achieve a similar performance as the simulated three-stage comparator without feed-forward (Fig.…”

“…5), while [19] is expected to perform similarly to the designed SAC (Table I). Regarding [20], it is questionable whether it can achieve data rates higher than a few GHz, or small enough delay variations due to its dynamic-bias pre-amplifier topology. Finally, [18] is expected to perform similarly to the designed DTC (Table I).…”