A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-$\mu{\rm m}$ CMOS Technology

Park, Jun‐Seok; Kim, Hyoeun; Kim, Lee-Sup

doi:10.1109/tcsvt.2012.2223873

Cited by 27 publications

(14 citation statements)

References 29 publications

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“…As proven in the [20], the case of keypoint test is always ended earlier than the non-keypoint cases. However, most of the pixels in regular images are not keypoints.…”

Section: ) String Searching Based Corner Detectormentioning

confidence: 87%

“…For example, BRIEF is deployed on the embedded SoC (System on Chip) in [19], and the processing speed on 1280*720 image achieves 60 fps (frame per second). 94.3 fps in 1080p full HD resolution at 200 MHz operating frequency is achieved in [20] by implementing a heterogeneous many-core system based on FAST (Features from Accelerated Segment Test) [21] and BRIEF. Although faster processing is enabled on these platforms, they are implemented at the cost of lower recognition performance under image distortions (such as image rotation and scaling).…”

Section: B Binary Descriptorsmentioning

confidence: 99%

“…In the image recognition accelerator proposed in [20], a novel segment test method, which is optimized based on the string searching algorithm is utilized to implement the interest point detection. Following the same principle, a new string searching algorithm-based corner detector is customized according to the requirements of the L-BIRD algorithm.…”

Section: ) String Searching Based Corner Detectormentioning

confidence: 99%

“…The position of the consecutive string is described by start_id and end_id. Different from the solution in [20], the next bit adjacent to the window end is also taken into consideration in shift distance calculation. Since the position information of the continuous string is required to compute the score and estimate the orientation of each keypoint in the L-BIRD algorithm, this value should also be considered in the proposed segment test.…”

Section: ) String Searching Based Corner Detectormentioning

confidence: 99%

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A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Zhu

Liu

Jiang

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

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Binary image descriptors, which derive image feature description from the local image patches directly, are widely adopted in the mobile and embedded applications due to lower computational complexity and memory requirement. With the aim of improving the computation efficiency without degrading recognition performance, a light-weight binary robust descriptor (L-BIRD) is proposed based on the analysis of the state-of-the-art binary descriptors in this paper. A directional edge detection and optimized keypoint score function are developed to refine the keypoints. In addition, rotation invariance is achieved by executing a circular symmetric based descriptor generation and a coarse-grained orientation calculation method concurrently. Experimental results demonstrate that the proposed keypoint detector and binary descriptor achieve more than 2 times speedup and at least 23.6% improvement in processing speed with comparable performance respectively. Furthermore, a VLSI architecture is also designed based on in-depth exploration of bit-level and task-level parallelism. Based on the post-layout simulation in TSMC 65 nm CMOS process, the accelerator can achieve 135 frames per second (fps) on 1080p image while only consuming 87.5 mW at 200 MHz operating frequency.

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“…As proven in the [20], the case of keypoint test is always ended earlier than the non-keypoint cases. However, most of the pixels in regular images are not keypoints.…”

Section: ) String Searching Based Corner Detectormentioning

confidence: 87%

Section: B Binary Descriptorsmentioning

confidence: 99%

Section: ) String Searching Based Corner Detectormentioning

confidence: 99%

Section: ) String Searching Based Corner Detectormentioning

confidence: 99%

See 2 more Smart Citations

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

Zhu

Liu

Jiang

et al. 2016

IEEE Trans. Circuits Syst. Video Technol.

View full text Add to dashboard Cite

show abstract

“…But to our knowledge, the following two are the only other FPGA/ASIC implementations of complete feature extraction and matching systems which are based on binary descriptors. J. S. Park, et al [16] implemented a variant of BRIEF with FAST keypoints [17] on an ASIC that has a throughput 94.3 full-HD frames per second with 512 extracted feature points per frame. J. Wang, et al [25] propose a FPGA system which is also based on BRIEF, but with SIFT keypoints.…”

Section: Related Workmentioning

confidence: 99%

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized

Schaffner

Hager

Cavigelli

et al. 2015

IFIP Advances in Information and Communication Technology

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Energy Consumption of Visual Sensor Networks: Impact of Spatio-Temporal Coverage Based on Single-Hop Topologies

Redondi

Buranapanichkit

Cesana

et al. 2014

Lecture Notes in Computer Science

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Wireless visual sensor networks (VSNs) are expected to play a major role in future IEEE 802.15.4 personal area networks (PAN) under recently-established collision-free medium access control (MAC) protocols. In such environments, the trade-off between the number of camera sensors to deploy (spatial coverage) and the frame rate to use for each camera sensor (temporal coverage) plays a major role in the VSN energy consumption. In this paper, we address this aspect for single-hop VSNs, i.e. networks comprising independent and identical wireless visual sensor nodes connected to a collection node via a star topology. We derive analytic results for the energy-optimal spatio-temporal coverage parameters of such VSNs under a-priori known bounds for the minimum frame rate per sensor and the minimum and maximum possible number of nodes to deploy. Our results are parametric to the probability density function characterizing the data-production rate per node and the energy consumption parameters of the system of interest. Experimental results using TelosB motes under: a collision-free transmission protocol, the IEEE 802.15.4 PAN physical layer (CC2420 transceiver) and Monte-Carlo-generated data sets, reveal that our analytic results are within 7% of the energy consumption measurements for a wide range of settings. In addition, results obtained via a multimedia subsystem performing visual feature extraction in video frames show that the optimal spatio-temporal settings derived by the proposed framework allow for up to 48% of reduction of energy consumption in comparison to ad-hoc settings. As such, our analytic modeling is useful for early-stage studies of possible VSN deployments under collision-free MAC protocols prior to costly and time-consuming experiments in the field

show abstract

A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-$\mu{\rm m}$ CMOS Technology

Cited by 27 publications

References 29 publications

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

A 135-frames/s 1080p 87.5-mW Binary-Descriptor-Based Image Feature Extraction Accelerator

A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized

Energy Consumption of Visual Sensor Networks: Impact of Spatio-Temporal Coverage Based on Single-Hop Topologies

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