A 1GS/s low-power low-kickback noise comparator in CMOS process

Baradaranrezaeii, Ali; Abdollahi, Roozbeh; Hadidi, Khayrollah; Khoei, Abdollah

doi:10.1109/ecctd.2011.6043288

Cited by 9 publications

(5 citation statements)

References 2 publications

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“…The simulation method must simulate the actual behavior of the system and the factual events that may affect the precision of the operation. As the comparison process can be divided into some sub operations; like resetting the remained effect of the previous samples, evaluating the current sample to steer the output direction and latching the output data up to the digital levels [1]; the simulation method is to cover all these sub operations for a vast verity of the structures employed as a comparator. The simulation method has to imitate every post fabrication tests from different sights of view in order to evaluate the comparator in terms of the speed (sample rate), accuracy (resolution), power consumption, noise, clock feed through, kickback noise, offset, latency, result valid time, metastability and so on.…”

Section: Efficient Simulation Methods For the Comparatorsmentioning

confidence: 99%

“…Because in fast or slow corners the charging procedure becomes fast or slow respectively, and the most important outcome is, that in all conditions the latching sequence is postponed until the winner side charges up to turn on the corresponding current mirror. In some approaches more than one signal is required to determine the time period of different sequences (resetting, evaluating and latching) [1,[3][4][5][6]. Meanwhile in this structure there is no need for an additional controlling signal to determine the start and stop time of the evaluation period.…”

Section: Proposed Structurementioning

confidence: 99%

“…As mentioned, the proposed structure is suitable for low speed conditions but for high speed applications it is necessary to reset the previous sample effect and prepare it for the next comparison cycle rapidly. Mainly, in single stage comparators, three different sequences are to be performed; reset, evaluation and latch [1][2][3]. In this case, some accurately adjusted controlling signals should be generated which increases the system complexity.…”

Section: Proposed Structurementioning

confidence: 99%

“…In this case, some accurately adjusted controlling signals should be generated which increases the system complexity. Generally, to reset the previous status, a conventional method is to short the output nodes together using an MOS switch [1][2][3] where the definition of the switch size is a great challenge. The smaller the switch size the longer the resetting time, and on the other hand, utilizing bigger device introduces more capacitance to the output nodes which increases the duration of the evaluation and latching process, both of the choices mean more time is required for the comparison process to be accomplished.…”

Section: Proposed Structurementioning

confidence: 99%

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An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

Baradaranrezaeii

Shino

Hadidi

et al. 2015

Analog Integr Circ Sig Process

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In this paper a novel structure is presented as a voltage comparator, and a reliable offset cancellation technique is utilized as well. Moreover a comprehensive post layout simulation method is described to evaluate a vast verity of comparators in order to find out whether the designed structure will operate properly in the post fabrication (solid state) tests or not. A single stage architecture with a simple readout circuit leads to a low-offset lowpower high-speed high-resolution comparator which qualifies for VLSI applications such as image sensors. Applying the reliable offset cancellation technique makes it qualified for high performance applications like high-speed high-resolution ADCs. The proposed comparator is simulated through the mentioned method in 0.18 lm standard CMOS technology, and 0.5 mV of accuracy in 1 G sample per second is obtained with a power consumption of 110 lW (150 lW with offset cancellation circuit) where an introduced offset of about 10 mV is cancelled to lower than 220 lV as well.

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Section: Efficient Simulation Methods For the Comparatorsmentioning

confidence: 99%

Section: Proposed Structurementioning

confidence: 99%

Section: Proposed Structurementioning

confidence: 99%

Section: Proposed Structurementioning

confidence: 99%

See 2 more Smart Citations

An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

Baradaranrezaeii

Shino

Hadidi

et al. 2015

Analog Integr Circ Sig Process

Self Cite

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“…As an example, a 7-bit flash ADC which contains 2 7 -1 high speed comparators [14] that are designed for 1G comparison per second with required accuracy and minimum power consumption of 96.2 mW in ''TT'' is assumed. Process variation does deteriorate the comparators performance mainly and consequently the whole ADC.…”

Section: Examplementioning

confidence: 99%

An ANFIS based fuzzy controller for corner compensation

Baradaranrezaeii

Khalilzadegan

Zarei

et al. 2011

Analog Integr Circ Sig Process

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As threshold voltage of CMOS transistors is the main parameter that takes effect from process variations, in this paper a novel method for corner detection is presented which senses the variations of fabrication process through threshold voltage of the devices. A new general purpose 2-input, 2-output, 25 rules, ANFIS based fuzzy controller is proposed to compensate the variations subsequently. In this controller novel structures are presented for each block including membership function generator, Min-Max selector and defuzzifier. As an application, bias points of comparators of a typical flash ADC are controlled through introduced system in order to compensate the process variation effects and minimizing total power consumption consequently. Due to differential structures used in the architecture of the blocks, major part of the power supply noise is rejected. The Hspice (level 49) simulation results are given using a generic 0.35 lm standard CMOS technology parameters and power supply of 3.3 V with total power consumption of 15.6 mW for 7.4 MFLIPS. Because of simple and symmetrical circuitry, layout of the proposed controller is very compact, about 410 lm 9 210 lm.

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