A 1Mb DRAM with a folded capacitor cell structure

Chemical vapor deposited (CVD) tungsten silicide films were formed by a cold wall reactor. These films were annealed in N2 to investigate changes in resistivity, composition, thickness, and impurity. The change in resistivity after 1000~ annealing becomes larger as the film reaches the stoichiometric value. A composition change occurs in a film whose composition Si/W is more than 2.6. Excess Si in the WSi, films (x > 2.6) is segregated in the boundary between WSi~. and poly-Si. A thickness change of about 15% occurs after 1000~ annealing at WSi~.4 on SiO~; this value is smaller than the calculated value. F and H, which are impurities in WSi, films decrease gradually and diffuse into gate SiO~ after 1000~ annealing.Progress of metal oxide semiconductor (MOS) large scale integrated circuits (LSI) is remarkably fast. Since the one kilo bit dynamic random access memory (1 Kbit DRAM) was developed in 1970, integration has advanced 4 times every 3 years. Now, one mega bit (1 Mbit) DRAM has been manufactured as a trial. The design rule for 1 Mbit DRAM is 1.2-1.3 #m, and the cell area has become very small: ranging from 20 to 35 /~m ~. For this reason, new capacitor structures such as trench and stacked capacitors are used (1-4). TiSi~, TaSi~, and other refractory metal silicides with a base layer of poly-Si and refractory metals such as W are being used as interconnection materials.The reason for employing refractory metals or refractory metal silicides is that as the linewidth becomes narrower and line length longer, resulting in high densification of devices, the signal propagation delay times become larger with the usually used poly-Si interconnection. Currently, there are two methods for forming these films: the physical vapor deposition (PVD) method, and the chemical vapor deposition (CVD) method.Among these methods, the CVD method is frequently used because of good step coverage. For example, we refer to the studies on deposition of WSi2 films by plasma CVD (5, 6). The low pressure chemical vapor deposited WSi, film, developed by Brors et al., however, is beginning to be widely used because of lower contamination and resistivity (7). Detailed reports on resistivity and capacitance-voltage characteristics have already been written.Generally, electrical characteristics degrade in the reaction between poly-Si and SiO~ during high temperature annealing (8). Consequently, it is necessary to study reactions and composition changes which include changes of F and H in the WSi, film by annealing; the mechanism of change also needs to be studied. Hara, et at. reported that reaction between WSi, film and the reaction between poly-Si and SiO.2 begins at 1000~ (9).We report on the changes in resistivity, composition, and behavior of F and H as well as the decreasing film thickness after annealing. LOW PRESSURE WSi x CVD SYSTEM MASS FLOW F~CONTROLLER L WF6 He Sill 4 t EACTORIuLF He VALVEI PUMP VENT ~ RF Fig. 1. Schematic diagram of the cold wall CVD equipment ExperimentalWSi~ films were formed by cold wall CVD (see Fig. 1). WF6...

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“…[3] when WSi~ is crystallized (11) In the case of x < 2 Vwsi~ = 2 Vwsi.z + (1-2) Vw [5] The volume decrease of WSi~. is shown in Fig.…”

Section: Decreasing Of Film Thickness--the Volume Decrease Ofmentioning

confidence: 99%

“…There also arises a need to understand the impact of electron-beam resists on the polysilicon etching process as electron beams become increasingly employed for submicron patterning (3,4). In this study, we have investigated the influence of several of these resists on the etching process.…”

Section: Hewlett-packard Laboratories Palo Alto California 94304mentioning

confidence: 99%

Changes in Resistivity and Composition of Chemical Vapor Deposited Tungsten Silicide Films by Annealing

Shioya

Itoh

Kobayashi

et al. 1986

J. Electrochem. Soc.

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“…For higher density, main memory applications, the 1-device cell DRAM technology is used [60]. Despite this memory cell change, it is interesting to see in Figure 3 that, empirically, the performance of main memory chips follows the same general performance-size trend as the SRAM chips (see Tables 7 and 8 derived from data in references [61][62][63][64][65][66][67][68][69][70][71][72][73][74]. The data points on Figure 3 represent chips announced at different times using different technologies so that an exact comparison is not possible; nevertheless, the memory access time for IGFET or bipolar technology generally increases (degrades) about 0.6 decades for every decade increase in memory capac- ity.…”

Section: Historical Backgroundmentioning

confidence: 99%

Challenges in advanced semiconductor technology for high-performance and supercomputer applications

Osburn

Reisman

1987

J Supercomput

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This article provides a review of the capabilities, future directions, and technology challenges for semiconductor chips and packages as they apply to high-performance and supercomputer applications. Semiconductor chip technology has resulted in dramatic device density improvements over the last 20 years. Scaling theory predicts that continued improvements will be possible if the technological problems associated with patterning, doping, interconnection, density, yield, and cost can be solved. The issues associated with these challenges are discussed. Finally, the packaging needs to support advanced chip technologies are reviewed.

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“…Among these new cells, vertically structured cells [1, 3, 4, 8-10, 25, 26] having high Cs such as trench cells and stacked capacitor cells, are becoming increasingly important. In addition, a planar cell structure combined with thin Sio2 film operating at half VCC plate voltage [5,6,8,10,11] is also extremely efficient to obtain high Cs. A folded data line cell incorporating a multidivision data line and a half ycc precharge provides the lowest VN.…”

Section: Power Dissipationmentioning

confidence: 99%

“…The density of dynamic random-access memories (DRAMs) has quadrupled every three years. In line with this, the development of 1 Mb DRAMs [1][2][3][4][5][6][7][8][9][10][11][12] as the next step from the existing 256 kb is already under way. This rapid evolution in DRAMs has been realized mainly by the progress in photolithography and onedevice cell.…”

mentioning

confidence: 99%