2012 7th International Symposium on Turbo Codes and Iterative Information Processing (ISTC) 2012
DOI: 10.1109/istc.2012.6325191
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A 2.15GBit/s turbo code decoder for LTE advanced base station applications

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Cited by 41 publications
(72 citation statements)
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“…The first method we will discuss is pipelining, which is employed extensively within the architectures of [48], [51], [52]. Pipelining reduces the critical path between two registers by adding additional registers to the middle of this path.…”
Section: A Data Path Considerationsmentioning
confidence: 99%
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“…The first method we will discuss is pipelining, which is employed extensively within the architectures of [48], [51], [52]. Pipelining reduces the critical path between two registers by adding additional registers to the middle of this path.…”
Section: A Data Path Considerationsmentioning
confidence: 99%
“…Figure 12 shows an example of pipelining in the turbo decoder of [51], which uses a similar decoder core to that proposed by the authors of [46], [49]. High-throughput turbo decoders, such as those proposed by [49], [52], [53], typically employ a multitude of these cores in parallel. The architecture of Figure 12 employs separate hardware units for calculating the α (forward state-metrics) and β (reverse state-metrics), each having dedicated hardware for generating the γ values.…”
Section: A Data Path Considerationsmentioning
confidence: 99%
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“…In [12], the parallelism of the Log-MAP algorithm was increased by decomposing the trellis into K number of sub-trellises and performing the Log-MAP algorithm on each in parallel, hence reducing the corresponding processing time by a factor of 1/K. Other approaches include pipelining the operations of the Log-MAP algorithm [13], so that different operations are performed in parallel, in different parts of the decoding hardware. Similarly, the radix-4 technique can be employed for processing two trellis stages at a time [13].…”
Section: Introductionmentioning
confidence: 99%
“…Other approaches include pipelining the operations of the Log-MAP algorithm [13], so that different operations are performed in parallel, in different parts of the decoding hardware. Similarly, the radix-4 technique can be employed for processing two trellis stages at a time [13]. Furthermore, some of the Log-MAP calculations can be replaced with lower-complexity approximations [11], so that a greater number of these calculations can be performed in parallel using the same amount of hardware.…”
Section: Introductionmentioning
confidence: 99%