A 2.2-&lt;inline-formula&gt; 
                     &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt;
                  &lt;/inline-formula&gt;W Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes

Rovere, Giovanni; Fateh, Schekeb; Benini, Luca

doi:10.1109/jetcas.2018.2828505

Cited by 32 publications

(12 citation statements)

References 23 publications

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“…The pole frequency is proportional to the the inverse of the pre-amplifier output resistance and, thus, it is proportional to the actual bias current 𝐼. Therefore, one can write , (7) where 𝐵𝑊 is the maximum pre-amplifier bandwidth, which is achieved for the maximum bias current 𝐼 . This equation is plotted in the lowest panel of Fig.…”

Section: B Noise Power and Gain Tradeoffsmentioning

confidence: 99%

See 1 more Smart Citation

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

Timmermans,

van Oosterhout,

Fattori

et al. 2024

IEEE J. Solid-State Circuits

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Section: B Noise Power and Gain Tradeoffsmentioning

confidence: 99%

“…In [6] an LC-ADC is used to compress the data generated by sensors that mimic the human skin. In [7]- [9], an LC-ADC is used as a wake-up detector for a more power-hungry system when activity is detected.…”

mentioning

confidence: 99%

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

Timmermans,

van Oosterhout,

Fattori

et al. 2024

IEEE J. Solid-State Circuits

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show abstract

“…Due to their event-driven behavior, asynchronous circuits are a promising approach to implement fast and reactive wake-up schemes but also environment aware duty-cycling of IoT applications [13]. In highly changing environments and low activity contexts, a clock-less processor implemented in asynchronous logic is a relevant solution which offers reduced power consumption, high robustness to operating conditions and short reactivity [14] [15].…”

Section: A Power Consumptionmentioning

confidence: 99%

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

Miro-Panades

Tain

Christmann

et al. 2023

IEEE J. Solid-State Circuits

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Increased capabilities such as recognition and selfadaptability are now required from IoT applications. While IoT node power consumption is a major concern for these applications, cloud-based processing is becoming unsustainable due to continuous sensor or image data transmission over the wireless network. Thus optimized ML capabilities and data transfers should be integrated in the IoT node. Moreover, IoT applications are torn between sporadic data-logging and energy-hungry data processing (e.g. image classification). Thus, the versatility of the node is key in addressing this wide diversity of energy and processing needs. This paper presents SamurAI, a versatile IoT node bridging this gap in processing and in energy by leveraging two on-chip sub-systems: a low power, clock-less, event-driven Always-Responsive (AR) part and an energy-efficient On-Demand (OD) part. AR contains a 1.7MOPS event-driven, asynchronous Wake-up Controller (WuC) with a 207ns wake-up time optimized for sporadic computing, while OD combines a deep-sleep RISC-V CPU and 1.3TOPS/W Machine Learning (ML) for more complex tasks up to 36GOPS. This architecture partitioning achieves best in class versatility metrics such as peak performance to idle power ratio. On an applicative classification scenario, it demonstrates system power gains, up to 3.5x compared to cloud-based processing, and thus extended battery lifetime.

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“…Refs. [14,15] report on a wake-up circuit based on LC-ADC and pattern recognition. It can be utilized in wearable devices and consumes only 2.1 µW at a 2.6 kHz bandwidth.…”

Section: Introductionmentioning

confidence: 99%

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

Tang,

Xu,

et al. 2024

Electronics

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This paper presents a level-crossing successive-approximation-register (LC-SAR) hybrid analog-to-digital converter (ADC) that combines an LC ADC with an SAR ADC, which may be used for Internet of Things (IoT) random sparse event scenarios. The sampling frequency of a traditional LC ADC is usually proportional to the maximum instantaneous rate of change of the input signal; therefore, a higher input signal frequency inevitably leads to higher system power consumption. However, the proposed hybrid ADC uses the input level difference between the two moments before and after level-crossing detection, thereby ensuring a higher conversion precision and lower power consumption, even at higher input signal frequencies. Compared with traditional LC ADC or SAR ADC, the proposed hybrid ADC combines the ultralow-power advantage of LC ADC with the high-precision advantage of SAR ADC in converting IoT data with sparse characteristics such as ECG, EEG, and brain potential. The LC-SAR hybrid ADC is designed with a 0.18 μm CMOS process and consumes 4.34 μW at a 1.8 V supply voltage, achieving an SNDR of 67.41 dB and a bandwidth of 20 kHz. The spectrum analysis result was 10.85 ENOB when the input sinusoidal signal was 14.975 kHz. When inputted with an ECG signal, the system power consumption was as low as 0.49 μW. Furthermore, the proposed hybrid ADC obtained a good figure of merit, with FoMw and FoMs reaching 58.8 fJ/conv.steps and 164 dB, respectively. Compared to a conventional uniform sampling ADC, approximately 80% of the power savings and an 8x compression ratio can be achieved in physiological signal acquisition applications.

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A 2.2-<inline-formula> <tex-math notation="LaTeX">$\mu$ </tex-math> </inline-formula>W Cognitive Always-On Wake-Up Circuit for Event-Driven Duty-Cycling of IoT Sensor Nodes

Cited by 32 publications

References 23 publications

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

A 1.8–65 fJ/Conv.-Step 64-dB SNDR Continuous- Time Level Crossing ADC Exploiting Dynamic Self-Biasing Comparators

SamurAI: A Versatile IoT Node With Event-Driven Wake-Up and Embedded ML Acceleration

A 0.49–4.34 μW LC-SAR Hybrid ADC with a 10.85-Bit ENOB and 20 KS/s Bandwidth

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