A 2.2mW 12-bit 200MS/s 28nm CMOS Pipelined SAR ADC with Dynamic Register-Based High-Speed SAR Logic

Park, Jun-Sang; Jeon, Je-Min; Boo, Jun-Ho; Lee, Jae-Hyuk; Cho, Kang-Il; Kim, Ho-Jin; Ahn, Gil-Cho; Lee, Seung‐Hoon

doi:10.1109/a-sscc48613.2020.9336146

Cited by 3 publications

(2 citation statements)

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“…The successive approximation register analogue-to-digital converter (SAR ADC) is the most power- and area-efficient architecture to attain 8~12-bit resolution [ 1 , 2 ], while its conversion speed is limited due to the inherent serial conversion process. The pipeline-SAR ADC splits the SAR ADC into two stages and connects them with an amplifier to realize pipelined operation, not only reducing conversion time, but also suppressing the comparator noise [ 3 , 4 ]. However, the induced inter-stage gain error and inevitable capacitor mismatch error cause bit-weight errors and, thus, degrade ADC performance.…”

Section: Introductionmentioning

confidence: 99%

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

Wang

Wan

et al. 2023

Micromachines

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This brief proposes a signal-independent background calibration in pipeline-SAR analog-to-digital converters (ADCs) with a convergence-accelerated technique. To achieve signal independence, an auxiliary capacitor array CA is introduced to pre-inject a pseudo-random noise (PN) in the sampling phase to cancel out the opposite PN injection of the calibrated capacitor in the conversion phase, and CA is also used to realize the D/A function of the calibrated capacitor in the conversion phase. In this way, no matter what the signal is, the residue headroom remains unchanged even with PN injection. Moreover, the first sub-ADC is designed with extended conversion bits to quantize its own residue after delivering the conversion bits required by the first stage. Afterwards, this result is provided to the calibration algorithm to reduce the signal component and accelerate the convergence. Based on the simulation, the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) improve from 45.3 dB and 56.4 dB to 68.2 dB and 88.4 dB, respectively, after calibration. In addition, with the acceleration technique, convergence cycles decrease from 1.7 × 108 to 5.8 × 106. Moreover, no matter whether the input signal is DC, sine wave or band-limited white noise, the calibration all works normally.

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Section: Introductionmentioning

confidence: 99%

Signal-Independent Background Calibration with Fast Convergence Speed in Pipeline-SAR ADC

Wang

Wan

et al. 2023

Micromachines

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“…The ADC is a key circuit for interface between analog and digital worlds [1,2,3]. Much attention has been paid to the SAR ADC due to small chip area and low power as well as no need for operational amplifier [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18], and its figure of merits (FOM) has been improved. The Hopfield network has been investigated as an ADC architecture for several tens of years [19,20,21,22,23,24], but it has not been widely used in practice.…”

Section: Introductionmentioning

confidence: 99%

Asynchronous capacitive SAR ADC based on Hopfield network

Bai

Katayama

Yao

et al. 2022

IEICE Electron. Express

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This letter revisits a Hopfield network for an SAR ADC configuration, which enables low voltage, low power and fast operation with small circuitry. It employs an asymmetrical Hopfield network to avoid local minimum, and it uses capacitors and switches instead of very large resistors. Our N-bit SAR ADC uses N chopper-type comparators with asynchronous parallel operation, which is different from the conventional asynchronous SAR ADC employing only one comparator. It requires only the sampling clock for each input data sampling; no internal high frequency clock is required. Its AD conversion time is determined only by the comparator delays and the capacitor charge/discharge settling times; hence it is very fast and the AD conversion latency is only one or two clock cycles. Its operation is verified with SPICE simulations.

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