A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process

Abstract

A 2.4GHz linear CMOS power amplifier (PA) for OFDM WLAN application in 65nm CMOS technology is presented. The cascode PA operating from 3.3V employs the proposed asymmetric lightly doped drain MOSFET (A-LDD) structure as common-gate stage to sustain large signal stress and 1.2V core device as common source stage to provide high frequency operation. Beside, dynamic bias technique is used not only to increase efficiency but also improve the linearity. In the measurement, the breakdown voltage of the A-LDD MOSFET can achieve 6.2V compared to standard I/O device of 5V. A PA EVM of -29dB is achieved at output power of 17dBm with DC current of 173mA from 3.3V supply. Also, it reveals the output P1dB of PA is 25.3dBm.